commit 8b8fc5a2357b177bfef61a7bf29a5148f60ce1bd Author: zx Date: Thu Apr 9 10:44:54 2026 +0800 init: 单进单出的sdarm diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..e243143 --- /dev/null +++ b/.gitignore @@ -0,0 +1,36 @@ +# Quartus Prime Generated Folders +db/ +incremental_db/ +output_files/ +simulation/ +greybox_tmp/ +hc_output/ +hps_isw_handoff/ +.qsys_edit/ + +# Quartus Prime Project Files to Ignore +*.qws +*.done +*.jdi +*.txt +*.rpt +*.summary +*.smsg +*.v.bak +*.qsf.bak +*.qpf.bak + +# Compilation artifacts +*.sof +*.pof +*.ttf +*.rbf +*.hex +*.jic +*.map +*.pin + +# EDA/Simulation artifacts +*.vo +*.vho +*.sdo diff --git a/MyCustomSdramTop.v b/MyCustomSdramTop.v new file mode 100644 index 0000000..09fe98e --- /dev/null +++ b/MyCustomSdramTop.v @@ -0,0 +1,1474 @@ +// Generator : SpinalHDL v1.10.1 git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43 +// Component : MyCustomSdramTop + +`timescale 1ns/1ps + +module MyCustomSdramTop ( + output wire [12:0] io_sdram_ADDR, + output wire [1:0] io_sdram_BA, + input wire [15:0] io_sdram_DQ_read, + output wire [15:0] io_sdram_DQ_write, + output wire [15:0] io_sdram_DQ_writeEnable, + output wire [1:0] io_sdram_DQM, + output wire io_sdram_CASn, + output wire io_sdram_CKE, + output wire io_sdram_CSn, + output wire io_sdram_RASn, + output wire io_sdram_WEn, + input wire io_userCmdValid, + output wire io_userCmdReady, + input wire io_userIsWrite, + input wire [23:0] io_userAddress, + input wire [15:0] io_userWriteData, + input wire [1:0] io_userWriteMask, + output wire io_userRspValid, + output wire [15:0] io_userRspData, + input wire clk, + input wire reset +); + + wire sdramCtrl_1_io_bus_cmd_payload_context; + wire sdramCtrl_1_io_bus_rsp_ready; + wire sdramCtrl_1_io_bus_cmd_ready; + wire sdramCtrl_1_io_bus_rsp_valid; + wire [15:0] sdramCtrl_1_io_bus_rsp_payload_data; + wire sdramCtrl_1_io_bus_rsp_payload_context; + wire [12:0] sdramCtrl_1_io_sdram_ADDR; + wire [1:0] sdramCtrl_1_io_sdram_BA; + wire sdramCtrl_1_io_sdram_CASn; + wire sdramCtrl_1_io_sdram_CKE; + wire sdramCtrl_1_io_sdram_CSn; + wire [1:0] sdramCtrl_1_io_sdram_DQM; + wire sdramCtrl_1_io_sdram_RASn; + wire sdramCtrl_1_io_sdram_WEn; + wire [15:0] sdramCtrl_1_io_sdram_DQ_write; + wire [15:0] sdramCtrl_1_io_sdram_DQ_writeEnable; + + SdramCtrl sdramCtrl_1 ( + .io_bus_cmd_valid (io_userCmdValid ), //i + .io_bus_cmd_ready (sdramCtrl_1_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_address (io_userAddress[23:0] ), //i + .io_bus_cmd_payload_write (io_userIsWrite ), //i + .io_bus_cmd_payload_data (io_userWriteData[15:0] ), //i + .io_bus_cmd_payload_mask (io_userWriteMask[1:0] ), //i + .io_bus_cmd_payload_context (sdramCtrl_1_io_bus_cmd_payload_context ), //i + .io_bus_rsp_valid (sdramCtrl_1_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (sdramCtrl_1_io_bus_rsp_ready ), //i + .io_bus_rsp_payload_data (sdramCtrl_1_io_bus_rsp_payload_data[15:0]), //o + .io_bus_rsp_payload_context (sdramCtrl_1_io_bus_rsp_payload_context ), //o + .io_sdram_ADDR (sdramCtrl_1_io_sdram_ADDR[12:0] ), //o + .io_sdram_BA (sdramCtrl_1_io_sdram_BA[1:0] ), //o + .io_sdram_DQ_read (io_sdram_DQ_read[15:0] ), //i + .io_sdram_DQ_write (sdramCtrl_1_io_sdram_DQ_write[15:0] ), //o + .io_sdram_DQ_writeEnable (sdramCtrl_1_io_sdram_DQ_writeEnable[15:0]), //o + .io_sdram_DQM (sdramCtrl_1_io_sdram_DQM[1:0] ), //o + .io_sdram_CASn (sdramCtrl_1_io_sdram_CASn ), //o + .io_sdram_CKE (sdramCtrl_1_io_sdram_CKE ), //o + .io_sdram_CSn (sdramCtrl_1_io_sdram_CSn ), //o + .io_sdram_RASn (sdramCtrl_1_io_sdram_RASn ), //o + .io_sdram_WEn (sdramCtrl_1_io_sdram_WEn ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_sdram_ADDR = sdramCtrl_1_io_sdram_ADDR; + assign io_sdram_BA = sdramCtrl_1_io_sdram_BA; + assign io_sdram_DQ_write = sdramCtrl_1_io_sdram_DQ_write; + assign io_sdram_DQ_writeEnable = sdramCtrl_1_io_sdram_DQ_writeEnable; + assign io_sdram_DQM = sdramCtrl_1_io_sdram_DQM; + assign io_sdram_CASn = sdramCtrl_1_io_sdram_CASn; + assign io_sdram_CKE = sdramCtrl_1_io_sdram_CKE; + assign io_sdram_CSn = sdramCtrl_1_io_sdram_CSn; + assign io_sdram_RASn = sdramCtrl_1_io_sdram_RASn; + assign io_sdram_WEn = sdramCtrl_1_io_sdram_WEn; + assign io_userCmdReady = sdramCtrl_1_io_bus_cmd_ready; + assign sdramCtrl_1_io_bus_cmd_payload_context = 1'b0; + assign io_userRspValid = sdramCtrl_1_io_bus_rsp_valid; + assign io_userRspData = sdramCtrl_1_io_bus_rsp_payload_data; + assign sdramCtrl_1_io_bus_rsp_ready = 1'b1; + +endmodule + +module SdramCtrl ( + input wire io_bus_cmd_valid, + output reg io_bus_cmd_ready, + input wire [23:0] io_bus_cmd_payload_address, + input wire io_bus_cmd_payload_write, + input wire [15:0] io_bus_cmd_payload_data, + input wire [1:0] io_bus_cmd_payload_mask, + input wire io_bus_cmd_payload_context, + output wire io_bus_rsp_valid, + input wire io_bus_rsp_ready, + output wire [15:0] io_bus_rsp_payload_data, + output wire io_bus_rsp_payload_context, + output wire [12:0] io_sdram_ADDR, + output wire [1:0] io_sdram_BA, + input wire [15:0] io_sdram_DQ_read, + output wire [15:0] io_sdram_DQ_write, + output wire [15:0] io_sdram_DQ_writeEnable, + output wire [1:0] io_sdram_DQM, + output wire io_sdram_CASn, + output wire io_sdram_CKE, + output wire io_sdram_CSn, + output wire io_sdram_RASn, + output wire io_sdram_WEn, + input wire clk, + input wire reset +); + localparam SdramCtrlBackendTask_MODE = 3'd0; + localparam SdramCtrlBackendTask_PRECHARGE_ALL = 3'd1; + localparam SdramCtrlBackendTask_PRECHARGE_SINGLE = 3'd2; + localparam SdramCtrlBackendTask_REFRESH = 3'd3; + localparam SdramCtrlBackendTask_ACTIVE = 3'd4; + localparam SdramCtrlBackendTask_READ = 3'd5; + localparam SdramCtrlBackendTask_WRITE = 3'd6; + localparam SdramCtrlFrontendState_BOOT_PRECHARGE = 2'd0; + localparam SdramCtrlFrontendState_BOOT_REFRESH = 2'd1; + localparam SdramCtrlFrontendState_BOOT_MODE = 2'd2; + localparam SdramCtrlFrontendState_RUN = 2'd3; + + wire chip_backupIn_fifo_io_flush; + wire chip_backupIn_fifo_io_push_ready; + wire chip_backupIn_fifo_io_pop_valid; + wire [15:0] chip_backupIn_fifo_io_pop_payload_data; + wire chip_backupIn_fifo_io_pop_payload_context; + wire [1:0] chip_backupIn_fifo_io_occupancy; + wire [1:0] chip_backupIn_fifo_io_availability; + wire [9:0] _zz_refresh_counter_valueNext; + wire [0:0] _zz_refresh_counter_valueNext_1; + wire [2:0] _zz_frontend_bootRefreshCounter_valueNext; + wire [0:0] _zz_frontend_bootRefreshCounter_valueNext_1; + reg _zz__zz_when_SdramCtrl_l224; + reg [12:0] _zz_when_SdramCtrl_l224_1; + reg _zz_bubbleInserter_insertBubble; + reg _zz_bubbleInserter_insertBubble_1; + wire refresh_counter_willIncrement; + wire refresh_counter_willClear; + reg [9:0] refresh_counter_valueNext; + reg [9:0] refresh_counter_value; + wire refresh_counter_willOverflowIfInc; + wire refresh_counter_willOverflow; + reg refresh_pending; + reg [14:0] powerup_counter; + reg powerup_done; + wire when_SdramCtrl_l146; + wire [14:0] _zz_when_SdramCtrl_l148; + wire when_SdramCtrl_l148; + reg frontend_banks_0_active; + reg [12:0] frontend_banks_0_row; + reg frontend_banks_1_active; + reg [12:0] frontend_banks_1_row; + reg frontend_banks_2_active; + reg [12:0] frontend_banks_2_row; + reg frontend_banks_3_active; + reg [12:0] frontend_banks_3_row; + wire [8:0] frontend_address_column; + wire [1:0] frontend_address_bank; + wire [12:0] frontend_address_row; + wire [23:0] _zz_frontend_address_column; + reg frontend_rsp_valid; + reg frontend_rsp_ready; + reg [2:0] frontend_rsp_payload_task; + wire [1:0] frontend_rsp_payload_bank; + reg [12:0] frontend_rsp_payload_rowColumn; + wire [15:0] frontend_rsp_payload_data; + wire [1:0] frontend_rsp_payload_mask; + wire frontend_rsp_payload_context; + reg [1:0] frontend_state; + reg frontend_bootRefreshCounter_willIncrement; + wire frontend_bootRefreshCounter_willClear; + reg [2:0] frontend_bootRefreshCounter_valueNext; + reg [2:0] frontend_bootRefreshCounter_value; + wire frontend_bootRefreshCounter_willOverflowIfInc; + wire frontend_bootRefreshCounter_willOverflow; + wire when_SdramCtrl_l210; + wire _zz_when_SdramCtrl_l224; + wire [3:0] _zz_1; + wire _zz_2; + wire _zz_3; + wire _zz_4; + wire _zz_5; + wire when_SdramCtrl_l224; + wire [2:0] _zz_frontend_rsp_payload_task; + wire when_SdramCtrl_l229; + wire bubbleInserter_cmd_valid; + wire bubbleInserter_cmd_ready; + wire [2:0] bubbleInserter_cmd_payload_task; + wire [1:0] bubbleInserter_cmd_payload_bank; + wire [12:0] bubbleInserter_cmd_payload_rowColumn; + wire [15:0] bubbleInserter_cmd_payload_data; + wire [1:0] bubbleInserter_cmd_payload_mask; + wire bubbleInserter_cmd_payload_context; + reg frontend_rsp_rValid; + reg [2:0] frontend_rsp_rData_task; + reg [1:0] frontend_rsp_rData_bank; + reg [12:0] frontend_rsp_rData_rowColumn; + reg [15:0] frontend_rsp_rData_data; + reg [1:0] frontend_rsp_rData_mask; + reg frontend_rsp_rData_context; + wire when_Stream_l369; + wire bubbleInserter_rsp_valid; + wire bubbleInserter_rsp_ready; + wire [2:0] bubbleInserter_rsp_payload_task; + wire [1:0] bubbleInserter_rsp_payload_bank; + wire [12:0] bubbleInserter_rsp_payload_rowColumn; + wire [15:0] bubbleInserter_rsp_payload_data; + wire [1:0] bubbleInserter_rsp_payload_mask; + wire bubbleInserter_rsp_payload_context; + reg bubbleInserter_insertBubble; + wire _zz_bubbleInserter_cmd_ready; + wire [2:0] _zz_bubbleInserter_rsp_payload_task; + reg [0:0] bubbleInserter_timings_read_counter; + wire bubbleInserter_timings_read_busy; + wire when_SdramCtrl_l256; + reg [2:0] bubbleInserter_timings_write_counter; + wire bubbleInserter_timings_write_busy; + wire when_SdramCtrl_l256_1; + reg [2:0] bubbleInserter_timings_banks_0_precharge_counter; + wire bubbleInserter_timings_banks_0_precharge_busy; + wire when_SdramCtrl_l256_2; + reg [2:0] bubbleInserter_timings_banks_0_active_counter; + wire bubbleInserter_timings_banks_0_active_busy; + wire when_SdramCtrl_l256_3; + reg [2:0] bubbleInserter_timings_banks_1_precharge_counter; + wire bubbleInserter_timings_banks_1_precharge_busy; + wire when_SdramCtrl_l256_4; + reg [2:0] bubbleInserter_timings_banks_1_active_counter; + wire bubbleInserter_timings_banks_1_active_busy; + wire when_SdramCtrl_l256_5; + reg [2:0] bubbleInserter_timings_banks_2_precharge_counter; + wire bubbleInserter_timings_banks_2_precharge_busy; + wire when_SdramCtrl_l256_6; + reg [2:0] bubbleInserter_timings_banks_2_active_counter; + wire bubbleInserter_timings_banks_2_active_busy; + wire when_SdramCtrl_l256_7; + reg [2:0] bubbleInserter_timings_banks_3_precharge_counter; + wire bubbleInserter_timings_banks_3_precharge_busy; + wire when_SdramCtrl_l256_8; + reg [2:0] bubbleInserter_timings_banks_3_active_counter; + wire bubbleInserter_timings_banks_3_active_busy; + wire when_SdramCtrl_l256_9; + wire when_SdramCtrl_l265; + wire when_SdramCtrl_l265_1; + wire when_SdramCtrl_l265_2; + wire when_SdramCtrl_l265_3; + wire when_SdramCtrl_l265_4; + wire when_Utils_l1017; + wire when_SdramCtrl_l265_5; + wire when_Utils_l1017_1; + wire when_SdramCtrl_l265_6; + wire when_Utils_l1017_2; + wire when_SdramCtrl_l265_7; + wire when_Utils_l1017_3; + wire when_SdramCtrl_l265_8; + wire when_SdramCtrl_l265_9; + wire when_SdramCtrl_l265_10; + wire when_SdramCtrl_l265_11; + wire when_SdramCtrl_l265_12; + wire when_SdramCtrl_l265_13; + wire when_Utils_l1017_4; + wire when_SdramCtrl_l265_14; + wire when_Utils_l1017_5; + wire when_SdramCtrl_l265_15; + wire when_Utils_l1017_6; + wire when_SdramCtrl_l265_16; + wire when_Utils_l1017_7; + wire when_SdramCtrl_l265_17; + wire when_Utils_l1017_8; + wire when_SdramCtrl_l265_18; + wire when_Utils_l1017_9; + wire when_SdramCtrl_l265_19; + wire when_Utils_l1017_10; + wire when_SdramCtrl_l265_20; + wire when_Utils_l1017_11; + wire when_SdramCtrl_l265_21; + wire when_SdramCtrl_l265_22; + wire when_Utils_l1017_12; + wire when_SdramCtrl_l265_23; + wire when_Utils_l1017_13; + wire when_SdramCtrl_l265_24; + wire when_Utils_l1017_14; + wire when_SdramCtrl_l265_25; + wire when_Utils_l1017_15; + wire when_SdramCtrl_l265_26; + wire chip_cmd_valid; + wire chip_cmd_ready; + wire [2:0] chip_cmd_payload_task; + wire [1:0] chip_cmd_payload_bank; + wire [12:0] chip_cmd_payload_rowColumn; + wire [15:0] chip_cmd_payload_data; + wire [1:0] chip_cmd_payload_mask; + wire chip_cmd_payload_context; + reg [12:0] chip_sdram_ADDR; + reg [1:0] chip_sdram_BA; + reg [15:0] chip_sdram_DQ_read; + reg [15:0] chip_sdram_DQ_write; + reg [15:0] chip_sdram_DQ_writeEnable; + reg [1:0] chip_sdram_DQM; + reg chip_sdram_CASn; + reg chip_sdram_CKE; + reg chip_sdram_CSn; + reg chip_sdram_RASn; + reg chip_sdram_WEn; + wire chip_remoteCke; + wire chip_readHistory_0; + wire chip_readHistory_1; + wire chip_readHistory_2; + wire chip_readHistory_3; + wire chip_readHistory_4; + wire chip_readHistory_5; + wire _zz_chip_readHistory_0; + reg _zz_chip_readHistory_1; + reg _zz_chip_readHistory_2; + reg _zz_chip_readHistory_3; + reg _zz_chip_readHistory_4; + reg _zz_chip_readHistory_5; + reg chip_cmd_payload_context_delay_1; + reg chip_cmd_payload_context_delay_2; + reg chip_cmd_payload_context_delay_3; + reg chip_cmd_payload_context_delay_4; + reg chip_contextDelayed; + wire chip_sdramCkeNext; + reg chip_sdramCkeInternal; + reg chip_sdramCkeInternal_regNext; + wire _zz_chip_sdram_DQM; + wire chip_backupIn_valid; + wire chip_backupIn_ready; + wire [15:0] chip_backupIn_payload_data; + wire chip_backupIn_payload_context; + `ifndef SYNTHESIS + reg [127:0] frontend_rsp_payload_task_string; + reg [111:0] frontend_state_string; + reg [127:0] _zz_frontend_rsp_payload_task_string; + reg [127:0] bubbleInserter_cmd_payload_task_string; + reg [127:0] frontend_rsp_rData_task_string; + reg [127:0] bubbleInserter_rsp_payload_task_string; + reg [127:0] _zz_bubbleInserter_rsp_payload_task_string; + reg [127:0] chip_cmd_payload_task_string; + `endif + + + assign _zz_refresh_counter_valueNext_1 = refresh_counter_willIncrement; + assign _zz_refresh_counter_valueNext = {9'd0, _zz_refresh_counter_valueNext_1}; + assign _zz_frontend_bootRefreshCounter_valueNext_1 = frontend_bootRefreshCounter_willIncrement; + assign _zz_frontend_bootRefreshCounter_valueNext = {2'd0, _zz_frontend_bootRefreshCounter_valueNext_1}; + StreamFifoLowLatency chip_backupIn_fifo ( + .io_push_valid (chip_backupIn_valid ), //i + .io_push_ready (chip_backupIn_fifo_io_push_ready ), //o + .io_push_payload_data (chip_backupIn_payload_data[15:0] ), //i + .io_push_payload_context (chip_backupIn_payload_context ), //i + .io_pop_valid (chip_backupIn_fifo_io_pop_valid ), //o + .io_pop_ready (io_bus_rsp_ready ), //i + .io_pop_payload_data (chip_backupIn_fifo_io_pop_payload_data[15:0]), //o + .io_pop_payload_context (chip_backupIn_fifo_io_pop_payload_context ), //o + .io_flush (chip_backupIn_fifo_io_flush ), //i + .io_occupancy (chip_backupIn_fifo_io_occupancy[1:0] ), //o + .io_availability (chip_backupIn_fifo_io_availability[1:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(frontend_address_bank) + 2'b00 : begin + _zz__zz_when_SdramCtrl_l224 = frontend_banks_0_active; + _zz_when_SdramCtrl_l224_1 = frontend_banks_0_row; + end + 2'b01 : begin + _zz__zz_when_SdramCtrl_l224 = frontend_banks_1_active; + _zz_when_SdramCtrl_l224_1 = frontend_banks_1_row; + end + 2'b10 : begin + _zz__zz_when_SdramCtrl_l224 = frontend_banks_2_active; + _zz_when_SdramCtrl_l224_1 = frontend_banks_2_row; + end + default : begin + _zz__zz_when_SdramCtrl_l224 = frontend_banks_3_active; + _zz_when_SdramCtrl_l224_1 = frontend_banks_3_row; + end + endcase + end + + always @(*) begin + case(bubbleInserter_cmd_payload_bank) + 2'b00 : begin + _zz_bubbleInserter_insertBubble = bubbleInserter_timings_banks_0_precharge_busy; + _zz_bubbleInserter_insertBubble_1 = bubbleInserter_timings_banks_0_active_busy; + end + 2'b01 : begin + _zz_bubbleInserter_insertBubble = bubbleInserter_timings_banks_1_precharge_busy; + _zz_bubbleInserter_insertBubble_1 = bubbleInserter_timings_banks_1_active_busy; + end + 2'b10 : begin + _zz_bubbleInserter_insertBubble = bubbleInserter_timings_banks_2_precharge_busy; + _zz_bubbleInserter_insertBubble_1 = bubbleInserter_timings_banks_2_active_busy; + end + default : begin + _zz_bubbleInserter_insertBubble = bubbleInserter_timings_banks_3_precharge_busy; + _zz_bubbleInserter_insertBubble_1 = bubbleInserter_timings_banks_3_active_busy; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(frontend_rsp_payload_task) + SdramCtrlBackendTask_MODE : frontend_rsp_payload_task_string = "MODE "; + SdramCtrlBackendTask_PRECHARGE_ALL : frontend_rsp_payload_task_string = "PRECHARGE_ALL "; + SdramCtrlBackendTask_PRECHARGE_SINGLE : frontend_rsp_payload_task_string = "PRECHARGE_SINGLE"; + SdramCtrlBackendTask_REFRESH : frontend_rsp_payload_task_string = "REFRESH "; + SdramCtrlBackendTask_ACTIVE : frontend_rsp_payload_task_string = "ACTIVE "; + SdramCtrlBackendTask_READ : frontend_rsp_payload_task_string = "READ "; + SdramCtrlBackendTask_WRITE : frontend_rsp_payload_task_string = "WRITE "; + default : frontend_rsp_payload_task_string = "????????????????"; + endcase + end + always @(*) begin + case(frontend_state) + SdramCtrlFrontendState_BOOT_PRECHARGE : frontend_state_string = "BOOT_PRECHARGE"; + SdramCtrlFrontendState_BOOT_REFRESH : frontend_state_string = "BOOT_REFRESH "; + SdramCtrlFrontendState_BOOT_MODE : frontend_state_string = "BOOT_MODE "; + SdramCtrlFrontendState_RUN : frontend_state_string = "RUN "; + default : frontend_state_string = "??????????????"; + endcase + end + always @(*) begin + case(_zz_frontend_rsp_payload_task) + SdramCtrlBackendTask_MODE : _zz_frontend_rsp_payload_task_string = "MODE "; + SdramCtrlBackendTask_PRECHARGE_ALL : _zz_frontend_rsp_payload_task_string = "PRECHARGE_ALL "; + SdramCtrlBackendTask_PRECHARGE_SINGLE : _zz_frontend_rsp_payload_task_string = "PRECHARGE_SINGLE"; + SdramCtrlBackendTask_REFRESH : _zz_frontend_rsp_payload_task_string = "REFRESH "; + SdramCtrlBackendTask_ACTIVE : _zz_frontend_rsp_payload_task_string = "ACTIVE "; + SdramCtrlBackendTask_READ : _zz_frontend_rsp_payload_task_string = "READ "; + SdramCtrlBackendTask_WRITE : _zz_frontend_rsp_payload_task_string = "WRITE "; + default : _zz_frontend_rsp_payload_task_string = "????????????????"; + endcase + end + always @(*) begin + case(bubbleInserter_cmd_payload_task) + SdramCtrlBackendTask_MODE : bubbleInserter_cmd_payload_task_string = "MODE "; + SdramCtrlBackendTask_PRECHARGE_ALL : bubbleInserter_cmd_payload_task_string = "PRECHARGE_ALL "; + SdramCtrlBackendTask_PRECHARGE_SINGLE : bubbleInserter_cmd_payload_task_string = "PRECHARGE_SINGLE"; + SdramCtrlBackendTask_REFRESH : bubbleInserter_cmd_payload_task_string = "REFRESH "; + SdramCtrlBackendTask_ACTIVE : bubbleInserter_cmd_payload_task_string = "ACTIVE "; + SdramCtrlBackendTask_READ : bubbleInserter_cmd_payload_task_string = "READ "; + SdramCtrlBackendTask_WRITE : bubbleInserter_cmd_payload_task_string = "WRITE "; + default : bubbleInserter_cmd_payload_task_string = "????????????????"; + endcase + end + always @(*) begin + case(frontend_rsp_rData_task) + SdramCtrlBackendTask_MODE : frontend_rsp_rData_task_string = "MODE "; + SdramCtrlBackendTask_PRECHARGE_ALL : frontend_rsp_rData_task_string = "PRECHARGE_ALL "; + SdramCtrlBackendTask_PRECHARGE_SINGLE : frontend_rsp_rData_task_string = "PRECHARGE_SINGLE"; + SdramCtrlBackendTask_REFRESH : frontend_rsp_rData_task_string = "REFRESH "; + SdramCtrlBackendTask_ACTIVE : frontend_rsp_rData_task_string = "ACTIVE "; + SdramCtrlBackendTask_READ : frontend_rsp_rData_task_string = "READ "; + SdramCtrlBackendTask_WRITE : frontend_rsp_rData_task_string = "WRITE "; + default : frontend_rsp_rData_task_string = "????????????????"; + endcase + end + always @(*) begin + case(bubbleInserter_rsp_payload_task) + SdramCtrlBackendTask_MODE : bubbleInserter_rsp_payload_task_string = "MODE "; + SdramCtrlBackendTask_PRECHARGE_ALL : bubbleInserter_rsp_payload_task_string = "PRECHARGE_ALL "; + SdramCtrlBackendTask_PRECHARGE_SINGLE : bubbleInserter_rsp_payload_task_string = "PRECHARGE_SINGLE"; + SdramCtrlBackendTask_REFRESH : bubbleInserter_rsp_payload_task_string = "REFRESH "; + SdramCtrlBackendTask_ACTIVE : bubbleInserter_rsp_payload_task_string = "ACTIVE "; + SdramCtrlBackendTask_READ : bubbleInserter_rsp_payload_task_string = "READ "; + SdramCtrlBackendTask_WRITE : bubbleInserter_rsp_payload_task_string = "WRITE "; + default : bubbleInserter_rsp_payload_task_string = "????????????????"; + endcase + end + always @(*) begin + case(_zz_bubbleInserter_rsp_payload_task) + SdramCtrlBackendTask_MODE : _zz_bubbleInserter_rsp_payload_task_string = "MODE "; + SdramCtrlBackendTask_PRECHARGE_ALL : _zz_bubbleInserter_rsp_payload_task_string = "PRECHARGE_ALL "; + SdramCtrlBackendTask_PRECHARGE_SINGLE : _zz_bubbleInserter_rsp_payload_task_string = "PRECHARGE_SINGLE"; + SdramCtrlBackendTask_REFRESH : _zz_bubbleInserter_rsp_payload_task_string = "REFRESH "; + SdramCtrlBackendTask_ACTIVE : _zz_bubbleInserter_rsp_payload_task_string = "ACTIVE "; + SdramCtrlBackendTask_READ : _zz_bubbleInserter_rsp_payload_task_string = "READ "; + SdramCtrlBackendTask_WRITE : _zz_bubbleInserter_rsp_payload_task_string = "WRITE "; + default : _zz_bubbleInserter_rsp_payload_task_string = "????????????????"; + endcase + end + always @(*) begin + case(chip_cmd_payload_task) + SdramCtrlBackendTask_MODE : chip_cmd_payload_task_string = "MODE "; + SdramCtrlBackendTask_PRECHARGE_ALL : chip_cmd_payload_task_string = "PRECHARGE_ALL "; + SdramCtrlBackendTask_PRECHARGE_SINGLE : chip_cmd_payload_task_string = "PRECHARGE_SINGLE"; + SdramCtrlBackendTask_REFRESH : chip_cmd_payload_task_string = "REFRESH "; + SdramCtrlBackendTask_ACTIVE : chip_cmd_payload_task_string = "ACTIVE "; + SdramCtrlBackendTask_READ : chip_cmd_payload_task_string = "READ "; + SdramCtrlBackendTask_WRITE : chip_cmd_payload_task_string = "WRITE "; + default : chip_cmd_payload_task_string = "????????????????"; + endcase + end + `endif + + assign refresh_counter_willClear = 1'b0; + assign refresh_counter_willOverflowIfInc = (refresh_counter_value == 10'h30d); + assign refresh_counter_willOverflow = (refresh_counter_willOverflowIfInc && refresh_counter_willIncrement); + always @(*) begin + if(refresh_counter_willOverflow) begin + refresh_counter_valueNext = 10'h000; + end else begin + refresh_counter_valueNext = (refresh_counter_value + _zz_refresh_counter_valueNext); + end + if(refresh_counter_willClear) begin + refresh_counter_valueNext = 10'h000; + end + end + + assign refresh_counter_willIncrement = 1'b1; + assign when_SdramCtrl_l146 = (! powerup_done); + assign _zz_when_SdramCtrl_l148[14 : 0] = 15'h7fff; + assign when_SdramCtrl_l148 = (powerup_counter == _zz_when_SdramCtrl_l148); + assign _zz_frontend_address_column = io_bus_cmd_payload_address; + assign frontend_address_column = _zz_frontend_address_column[8 : 0]; + assign frontend_address_bank = _zz_frontend_address_column[10 : 9]; + assign frontend_address_row = _zz_frontend_address_column[23 : 11]; + always @(*) begin + frontend_rsp_valid = 1'b0; + case(frontend_state) + SdramCtrlFrontendState_BOOT_PRECHARGE : begin + if(powerup_done) begin + frontend_rsp_valid = 1'b1; + end + end + SdramCtrlFrontendState_BOOT_REFRESH : begin + frontend_rsp_valid = 1'b1; + end + SdramCtrlFrontendState_BOOT_MODE : begin + frontend_rsp_valid = 1'b1; + end + default : begin + if(refresh_pending) begin + frontend_rsp_valid = 1'b1; + end else begin + if(io_bus_cmd_valid) begin + frontend_rsp_valid = 1'b1; + end + end + end + endcase + end + + always @(*) begin + frontend_rsp_payload_task = SdramCtrlBackendTask_REFRESH; + case(frontend_state) + SdramCtrlFrontendState_BOOT_PRECHARGE : begin + frontend_rsp_payload_task = SdramCtrlBackendTask_PRECHARGE_ALL; + end + SdramCtrlFrontendState_BOOT_REFRESH : begin + frontend_rsp_payload_task = SdramCtrlBackendTask_REFRESH; + end + SdramCtrlFrontendState_BOOT_MODE : begin + frontend_rsp_payload_task = SdramCtrlBackendTask_MODE; + end + default : begin + if(refresh_pending) begin + if(when_SdramCtrl_l210) begin + frontend_rsp_payload_task = SdramCtrlBackendTask_PRECHARGE_ALL; + end else begin + frontend_rsp_payload_task = SdramCtrlBackendTask_REFRESH; + end + end else begin + if(io_bus_cmd_valid) begin + if(when_SdramCtrl_l224) begin + frontend_rsp_payload_task = SdramCtrlBackendTask_PRECHARGE_SINGLE; + end else begin + if(when_SdramCtrl_l229) begin + frontend_rsp_payload_task = SdramCtrlBackendTask_ACTIVE; + end else begin + frontend_rsp_payload_task = _zz_frontend_rsp_payload_task; + end + end + end + end + end + endcase + end + + assign frontend_rsp_payload_bank = frontend_address_bank; + always @(*) begin + frontend_rsp_payload_rowColumn = frontend_address_row; + case(frontend_state) + SdramCtrlFrontendState_BOOT_PRECHARGE : begin + end + SdramCtrlFrontendState_BOOT_REFRESH : begin + end + SdramCtrlFrontendState_BOOT_MODE : begin + end + default : begin + if(!refresh_pending) begin + if(io_bus_cmd_valid) begin + if(!when_SdramCtrl_l224) begin + if(!when_SdramCtrl_l229) begin + frontend_rsp_payload_rowColumn = {4'd0, frontend_address_column}; + end + end + end + end + end + endcase + end + + assign frontend_rsp_payload_data = io_bus_cmd_payload_data; + assign frontend_rsp_payload_mask = io_bus_cmd_payload_mask; + assign frontend_rsp_payload_context = io_bus_cmd_payload_context; + always @(*) begin + io_bus_cmd_ready = 1'b0; + case(frontend_state) + SdramCtrlFrontendState_BOOT_PRECHARGE : begin + end + SdramCtrlFrontendState_BOOT_REFRESH : begin + end + SdramCtrlFrontendState_BOOT_MODE : begin + end + default : begin + if(!refresh_pending) begin + if(io_bus_cmd_valid) begin + if(!when_SdramCtrl_l224) begin + if(!when_SdramCtrl_l229) begin + io_bus_cmd_ready = frontend_rsp_ready; + end + end + end + end + end + endcase + end + + always @(*) begin + frontend_bootRefreshCounter_willIncrement = 1'b0; + case(frontend_state) + SdramCtrlFrontendState_BOOT_PRECHARGE : begin + end + SdramCtrlFrontendState_BOOT_REFRESH : begin + if(frontend_rsp_ready) begin + frontend_bootRefreshCounter_willIncrement = 1'b1; + end + end + SdramCtrlFrontendState_BOOT_MODE : begin + end + default : begin + end + endcase + end + + assign frontend_bootRefreshCounter_willClear = 1'b0; + assign frontend_bootRefreshCounter_willOverflowIfInc = (frontend_bootRefreshCounter_value == 3'b111); + assign frontend_bootRefreshCounter_willOverflow = (frontend_bootRefreshCounter_willOverflowIfInc && frontend_bootRefreshCounter_willIncrement); + always @(*) begin + frontend_bootRefreshCounter_valueNext = (frontend_bootRefreshCounter_value + _zz_frontend_bootRefreshCounter_valueNext); + if(frontend_bootRefreshCounter_willClear) begin + frontend_bootRefreshCounter_valueNext = 3'b000; + end + end + + assign when_SdramCtrl_l210 = (((frontend_banks_0_active || frontend_banks_1_active) || frontend_banks_2_active) || frontend_banks_3_active); + assign _zz_when_SdramCtrl_l224 = _zz__zz_when_SdramCtrl_l224; + assign _zz_1 = ({3'd0,1'b1} <<< frontend_address_bank); + assign _zz_2 = _zz_1[0]; + assign _zz_3 = _zz_1[1]; + assign _zz_4 = _zz_1[2]; + assign _zz_5 = _zz_1[3]; + assign when_SdramCtrl_l224 = (_zz_when_SdramCtrl_l224 && (_zz_when_SdramCtrl_l224_1 != frontend_address_row)); + assign _zz_frontend_rsp_payload_task = (io_bus_cmd_payload_write ? SdramCtrlBackendTask_WRITE : SdramCtrlBackendTask_READ); + assign when_SdramCtrl_l229 = (! _zz_when_SdramCtrl_l224); + always @(*) begin + frontend_rsp_ready = bubbleInserter_cmd_ready; + if(when_Stream_l369) begin + frontend_rsp_ready = 1'b1; + end + end + + assign when_Stream_l369 = (! bubbleInserter_cmd_valid); + assign bubbleInserter_cmd_valid = frontend_rsp_rValid; + assign bubbleInserter_cmd_payload_task = frontend_rsp_rData_task; + assign bubbleInserter_cmd_payload_bank = frontend_rsp_rData_bank; + assign bubbleInserter_cmd_payload_rowColumn = frontend_rsp_rData_rowColumn; + assign bubbleInserter_cmd_payload_data = frontend_rsp_rData_data; + assign bubbleInserter_cmd_payload_mask = frontend_rsp_rData_mask; + assign bubbleInserter_cmd_payload_context = frontend_rsp_rData_context; + always @(*) begin + bubbleInserter_insertBubble = 1'b0; + if(bubbleInserter_cmd_valid) begin + case(bubbleInserter_cmd_payload_task) + SdramCtrlBackendTask_MODE : begin + bubbleInserter_insertBubble = bubbleInserter_timings_banks_0_active_busy; + end + SdramCtrlBackendTask_PRECHARGE_ALL : begin + bubbleInserter_insertBubble = (|{bubbleInserter_timings_banks_3_precharge_busy,{bubbleInserter_timings_banks_2_precharge_busy,{bubbleInserter_timings_banks_1_precharge_busy,bubbleInserter_timings_banks_0_precharge_busy}}}); + end + SdramCtrlBackendTask_PRECHARGE_SINGLE : begin + bubbleInserter_insertBubble = _zz_bubbleInserter_insertBubble; + end + SdramCtrlBackendTask_REFRESH : begin + bubbleInserter_insertBubble = (|{bubbleInserter_timings_banks_3_active_busy,{bubbleInserter_timings_banks_2_active_busy,{bubbleInserter_timings_banks_1_active_busy,bubbleInserter_timings_banks_0_active_busy}}}); + end + SdramCtrlBackendTask_ACTIVE : begin + bubbleInserter_insertBubble = _zz_bubbleInserter_insertBubble_1; + end + SdramCtrlBackendTask_READ : begin + bubbleInserter_insertBubble = bubbleInserter_timings_read_busy; + end + default : begin + bubbleInserter_insertBubble = bubbleInserter_timings_write_busy; + end + endcase + end + end + + assign _zz_bubbleInserter_cmd_ready = (! bubbleInserter_insertBubble); + assign bubbleInserter_cmd_ready = (bubbleInserter_rsp_ready && _zz_bubbleInserter_cmd_ready); + assign _zz_bubbleInserter_rsp_payload_task = bubbleInserter_cmd_payload_task; + assign bubbleInserter_rsp_valid = (bubbleInserter_cmd_valid && _zz_bubbleInserter_cmd_ready); + assign bubbleInserter_rsp_payload_task = _zz_bubbleInserter_rsp_payload_task; + assign bubbleInserter_rsp_payload_bank = bubbleInserter_cmd_payload_bank; + assign bubbleInserter_rsp_payload_rowColumn = bubbleInserter_cmd_payload_rowColumn; + assign bubbleInserter_rsp_payload_data = bubbleInserter_cmd_payload_data; + assign bubbleInserter_rsp_payload_mask = bubbleInserter_cmd_payload_mask; + assign bubbleInserter_rsp_payload_context = bubbleInserter_cmd_payload_context; + assign bubbleInserter_timings_read_busy = (bubbleInserter_timings_read_counter != 1'b0); + assign when_SdramCtrl_l256 = (bubbleInserter_timings_read_busy && bubbleInserter_rsp_ready); + assign bubbleInserter_timings_write_busy = (bubbleInserter_timings_write_counter != 3'b000); + assign when_SdramCtrl_l256_1 = (bubbleInserter_timings_write_busy && bubbleInserter_rsp_ready); + assign bubbleInserter_timings_banks_0_precharge_busy = (bubbleInserter_timings_banks_0_precharge_counter != 3'b000); + assign when_SdramCtrl_l256_2 = (bubbleInserter_timings_banks_0_precharge_busy && bubbleInserter_rsp_ready); + assign bubbleInserter_timings_banks_0_active_busy = (bubbleInserter_timings_banks_0_active_counter != 3'b000); + assign when_SdramCtrl_l256_3 = (bubbleInserter_timings_banks_0_active_busy && bubbleInserter_rsp_ready); + assign bubbleInserter_timings_banks_1_precharge_busy = (bubbleInserter_timings_banks_1_precharge_counter != 3'b000); + assign when_SdramCtrl_l256_4 = (bubbleInserter_timings_banks_1_precharge_busy && bubbleInserter_rsp_ready); + assign bubbleInserter_timings_banks_1_active_busy = (bubbleInserter_timings_banks_1_active_counter != 3'b000); + assign when_SdramCtrl_l256_5 = (bubbleInserter_timings_banks_1_active_busy && bubbleInserter_rsp_ready); + assign bubbleInserter_timings_banks_2_precharge_busy = (bubbleInserter_timings_banks_2_precharge_counter != 3'b000); + assign when_SdramCtrl_l256_6 = (bubbleInserter_timings_banks_2_precharge_busy && bubbleInserter_rsp_ready); + assign bubbleInserter_timings_banks_2_active_busy = (bubbleInserter_timings_banks_2_active_counter != 3'b000); + assign when_SdramCtrl_l256_7 = (bubbleInserter_timings_banks_2_active_busy && bubbleInserter_rsp_ready); + assign bubbleInserter_timings_banks_3_precharge_busy = (bubbleInserter_timings_banks_3_precharge_counter != 3'b000); + assign when_SdramCtrl_l256_8 = (bubbleInserter_timings_banks_3_precharge_busy && bubbleInserter_rsp_ready); + assign bubbleInserter_timings_banks_3_active_busy = (bubbleInserter_timings_banks_3_active_counter != 3'b000); + assign when_SdramCtrl_l256_9 = (bubbleInserter_timings_banks_3_active_busy && bubbleInserter_rsp_ready); + assign when_SdramCtrl_l265 = (bubbleInserter_timings_banks_0_active_counter <= 3'b001); + assign when_SdramCtrl_l265_1 = (bubbleInserter_timings_banks_1_active_counter <= 3'b001); + assign when_SdramCtrl_l265_2 = (bubbleInserter_timings_banks_2_active_counter <= 3'b001); + assign when_SdramCtrl_l265_3 = (bubbleInserter_timings_banks_3_active_counter <= 3'b001); + assign when_SdramCtrl_l265_4 = (bubbleInserter_timings_banks_0_active_counter <= 3'b001); + assign when_Utils_l1017 = (bubbleInserter_cmd_payload_bank == 2'b00); + assign when_SdramCtrl_l265_5 = (bubbleInserter_timings_banks_0_active_counter <= 3'b001); + assign when_Utils_l1017_1 = (bubbleInserter_cmd_payload_bank == 2'b01); + assign when_SdramCtrl_l265_6 = (bubbleInserter_timings_banks_1_active_counter <= 3'b001); + assign when_Utils_l1017_2 = (bubbleInserter_cmd_payload_bank == 2'b10); + assign when_SdramCtrl_l265_7 = (bubbleInserter_timings_banks_2_active_counter <= 3'b001); + assign when_Utils_l1017_3 = (bubbleInserter_cmd_payload_bank == 2'b11); + assign when_SdramCtrl_l265_8 = (bubbleInserter_timings_banks_3_active_counter <= 3'b001); + assign when_SdramCtrl_l265_9 = (bubbleInserter_timings_banks_0_active_counter <= 3'b101); + assign when_SdramCtrl_l265_10 = (bubbleInserter_timings_banks_1_active_counter <= 3'b101); + assign when_SdramCtrl_l265_11 = (bubbleInserter_timings_banks_2_active_counter <= 3'b101); + assign when_SdramCtrl_l265_12 = (bubbleInserter_timings_banks_3_active_counter <= 3'b101); + assign when_SdramCtrl_l265_13 = (bubbleInserter_timings_write_counter <= 3'b001); + assign when_Utils_l1017_4 = (bubbleInserter_cmd_payload_bank == 2'b00); + assign when_SdramCtrl_l265_14 = (bubbleInserter_timings_banks_0_precharge_counter <= 3'b100); + assign when_Utils_l1017_5 = (bubbleInserter_cmd_payload_bank == 2'b01); + assign when_SdramCtrl_l265_15 = (bubbleInserter_timings_banks_1_precharge_counter <= 3'b100); + assign when_Utils_l1017_6 = (bubbleInserter_cmd_payload_bank == 2'b10); + assign when_SdramCtrl_l265_16 = (bubbleInserter_timings_banks_2_precharge_counter <= 3'b100); + assign when_Utils_l1017_7 = (bubbleInserter_cmd_payload_bank == 2'b11); + assign when_SdramCtrl_l265_17 = (bubbleInserter_timings_banks_3_precharge_counter <= 3'b100); + assign when_Utils_l1017_8 = (bubbleInserter_cmd_payload_bank == 2'b00); + assign when_SdramCtrl_l265_18 = (bubbleInserter_timings_banks_0_active_counter <= 3'b101); + assign when_Utils_l1017_9 = (bubbleInserter_cmd_payload_bank == 2'b01); + assign when_SdramCtrl_l265_19 = (bubbleInserter_timings_banks_1_active_counter <= 3'b101); + assign when_Utils_l1017_10 = (bubbleInserter_cmd_payload_bank == 2'b10); + assign when_SdramCtrl_l265_20 = (bubbleInserter_timings_banks_2_active_counter <= 3'b101); + assign when_Utils_l1017_11 = (bubbleInserter_cmd_payload_bank == 2'b11); + assign when_SdramCtrl_l265_21 = (bubbleInserter_timings_banks_3_active_counter <= 3'b101); + assign when_SdramCtrl_l265_22 = (bubbleInserter_timings_write_counter <= 3'b100); + assign when_Utils_l1017_12 = (bubbleInserter_cmd_payload_bank == 2'b00); + assign when_SdramCtrl_l265_23 = (bubbleInserter_timings_banks_0_precharge_counter <= 3'b001); + assign when_Utils_l1017_13 = (bubbleInserter_cmd_payload_bank == 2'b01); + assign when_SdramCtrl_l265_24 = (bubbleInserter_timings_banks_1_precharge_counter <= 3'b001); + assign when_Utils_l1017_14 = (bubbleInserter_cmd_payload_bank == 2'b10); + assign when_SdramCtrl_l265_25 = (bubbleInserter_timings_banks_2_precharge_counter <= 3'b001); + assign when_Utils_l1017_15 = (bubbleInserter_cmd_payload_bank == 2'b11); + assign when_SdramCtrl_l265_26 = (bubbleInserter_timings_banks_3_precharge_counter <= 3'b001); + assign chip_cmd_valid = bubbleInserter_rsp_valid; + assign bubbleInserter_rsp_ready = chip_cmd_ready; + assign chip_cmd_payload_task = bubbleInserter_rsp_payload_task; + assign chip_cmd_payload_bank = bubbleInserter_rsp_payload_bank; + assign chip_cmd_payload_rowColumn = bubbleInserter_rsp_payload_rowColumn; + assign chip_cmd_payload_data = bubbleInserter_rsp_payload_data; + assign chip_cmd_payload_mask = bubbleInserter_rsp_payload_mask; + assign chip_cmd_payload_context = bubbleInserter_rsp_payload_context; + assign io_sdram_ADDR = chip_sdram_ADDR; + assign io_sdram_BA = chip_sdram_BA; + assign io_sdram_DQ_write = chip_sdram_DQ_write; + assign io_sdram_DQ_writeEnable = chip_sdram_DQ_writeEnable; + assign io_sdram_DQM = chip_sdram_DQM; + assign io_sdram_CASn = chip_sdram_CASn; + assign io_sdram_CKE = chip_sdram_CKE; + assign io_sdram_CSn = chip_sdram_CSn; + assign io_sdram_RASn = chip_sdram_RASn; + assign io_sdram_WEn = chip_sdram_WEn; + assign _zz_chip_readHistory_0 = (chip_cmd_valid && ((chip_cmd_payload_task == SdramCtrlBackendTask_READ) || 1'b0)); + assign chip_readHistory_0 = _zz_chip_readHistory_0; + assign chip_readHistory_1 = _zz_chip_readHistory_1; + assign chip_readHistory_2 = _zz_chip_readHistory_2; + assign chip_readHistory_3 = _zz_chip_readHistory_3; + assign chip_readHistory_4 = _zz_chip_readHistory_4; + assign chip_readHistory_5 = _zz_chip_readHistory_5; + assign chip_sdramCkeNext = (! ((|{chip_readHistory_5,{chip_readHistory_4,{chip_readHistory_3,{chip_readHistory_2,{chip_readHistory_1,chip_readHistory_0}}}}}) && (! io_bus_rsp_ready))); + assign chip_remoteCke = chip_sdramCkeInternal_regNext; + assign _zz_chip_sdram_DQM = (! chip_readHistory_1); + assign chip_backupIn_valid = (chip_readHistory_5 && chip_remoteCke); + assign chip_backupIn_payload_data = chip_sdram_DQ_read; + assign chip_backupIn_payload_context = chip_contextDelayed; + assign chip_backupIn_ready = chip_backupIn_fifo_io_push_ready; + assign io_bus_rsp_valid = chip_backupIn_fifo_io_pop_valid; + assign io_bus_rsp_payload_data = chip_backupIn_fifo_io_pop_payload_data; + assign io_bus_rsp_payload_context = chip_backupIn_fifo_io_pop_payload_context; + assign chip_cmd_ready = chip_remoteCke; + assign chip_backupIn_fifo_io_flush = 1'b0; + always @(posedge clk or posedge reset) begin + if(reset) begin + refresh_counter_value <= 10'h000; + refresh_pending <= 1'b0; + powerup_counter <= 15'h0000; + powerup_done <= 1'b0; + frontend_banks_0_active <= 1'b0; + frontend_banks_1_active <= 1'b0; + frontend_banks_2_active <= 1'b0; + frontend_banks_3_active <= 1'b0; + frontend_state <= SdramCtrlFrontendState_BOOT_PRECHARGE; + frontend_bootRefreshCounter_value <= 3'b000; + frontend_rsp_rValid <= 1'b0; + bubbleInserter_timings_read_counter <= 1'b0; + bubbleInserter_timings_write_counter <= 3'b000; + bubbleInserter_timings_banks_0_precharge_counter <= 3'b000; + bubbleInserter_timings_banks_0_active_counter <= 3'b000; + bubbleInserter_timings_banks_1_precharge_counter <= 3'b000; + bubbleInserter_timings_banks_1_active_counter <= 3'b000; + bubbleInserter_timings_banks_2_precharge_counter <= 3'b000; + bubbleInserter_timings_banks_2_active_counter <= 3'b000; + bubbleInserter_timings_banks_3_precharge_counter <= 3'b000; + bubbleInserter_timings_banks_3_active_counter <= 3'b000; + _zz_chip_readHistory_1 <= 1'b0; + _zz_chip_readHistory_2 <= 1'b0; + _zz_chip_readHistory_3 <= 1'b0; + _zz_chip_readHistory_4 <= 1'b0; + _zz_chip_readHistory_5 <= 1'b0; + chip_sdramCkeInternal <= 1'b1; + chip_sdramCkeInternal_regNext <= 1'b1; + end else begin + refresh_counter_value <= refresh_counter_valueNext; + if(refresh_counter_willOverflow) begin + refresh_pending <= 1'b1; + end + if(when_SdramCtrl_l146) begin + powerup_counter <= (powerup_counter + 15'h0001); + if(when_SdramCtrl_l148) begin + powerup_done <= 1'b1; + end + end + frontend_bootRefreshCounter_value <= frontend_bootRefreshCounter_valueNext; + case(frontend_state) + SdramCtrlFrontendState_BOOT_PRECHARGE : begin + if(powerup_done) begin + if(frontend_rsp_ready) begin + frontend_state <= SdramCtrlFrontendState_BOOT_REFRESH; + end + end + end + SdramCtrlFrontendState_BOOT_REFRESH : begin + if(frontend_rsp_ready) begin + if(frontend_bootRefreshCounter_willOverflowIfInc) begin + frontend_state <= SdramCtrlFrontendState_BOOT_MODE; + end + end + end + SdramCtrlFrontendState_BOOT_MODE : begin + if(frontend_rsp_ready) begin + frontend_state <= SdramCtrlFrontendState_RUN; + end + end + default : begin + if(refresh_pending) begin + if(when_SdramCtrl_l210) begin + if(frontend_rsp_ready) begin + frontend_banks_0_active <= 1'b0; + frontend_banks_1_active <= 1'b0; + frontend_banks_2_active <= 1'b0; + frontend_banks_3_active <= 1'b0; + end + end else begin + if(frontend_rsp_ready) begin + refresh_pending <= 1'b0; + end + end + end else begin + if(io_bus_cmd_valid) begin + if(when_SdramCtrl_l224) begin + if(frontend_rsp_ready) begin + if(_zz_2) begin + frontend_banks_0_active <= 1'b0; + end + if(_zz_3) begin + frontend_banks_1_active <= 1'b0; + end + if(_zz_4) begin + frontend_banks_2_active <= 1'b0; + end + if(_zz_5) begin + frontend_banks_3_active <= 1'b0; + end + end + end else begin + if(when_SdramCtrl_l229) begin + if(frontend_rsp_ready) begin + if(_zz_2) begin + frontend_banks_0_active <= 1'b1; + end + if(_zz_3) begin + frontend_banks_1_active <= 1'b1; + end + if(_zz_4) begin + frontend_banks_2_active <= 1'b1; + end + if(_zz_5) begin + frontend_banks_3_active <= 1'b1; + end + end + end + end + end + end + end + endcase + if(frontend_rsp_ready) begin + frontend_rsp_rValid <= frontend_rsp_valid; + end + if(when_SdramCtrl_l256) begin + bubbleInserter_timings_read_counter <= (bubbleInserter_timings_read_counter - 1'b1); + end + if(when_SdramCtrl_l256_1) begin + bubbleInserter_timings_write_counter <= (bubbleInserter_timings_write_counter - 3'b001); + end + if(when_SdramCtrl_l256_2) begin + bubbleInserter_timings_banks_0_precharge_counter <= (bubbleInserter_timings_banks_0_precharge_counter - 3'b001); + end + if(when_SdramCtrl_l256_3) begin + bubbleInserter_timings_banks_0_active_counter <= (bubbleInserter_timings_banks_0_active_counter - 3'b001); + end + if(when_SdramCtrl_l256_4) begin + bubbleInserter_timings_banks_1_precharge_counter <= (bubbleInserter_timings_banks_1_precharge_counter - 3'b001); + end + if(when_SdramCtrl_l256_5) begin + bubbleInserter_timings_banks_1_active_counter <= (bubbleInserter_timings_banks_1_active_counter - 3'b001); + end + if(when_SdramCtrl_l256_6) begin + bubbleInserter_timings_banks_2_precharge_counter <= (bubbleInserter_timings_banks_2_precharge_counter - 3'b001); + end + if(when_SdramCtrl_l256_7) begin + bubbleInserter_timings_banks_2_active_counter <= (bubbleInserter_timings_banks_2_active_counter - 3'b001); + end + if(when_SdramCtrl_l256_8) begin + bubbleInserter_timings_banks_3_precharge_counter <= (bubbleInserter_timings_banks_3_precharge_counter - 3'b001); + end + if(when_SdramCtrl_l256_9) begin + bubbleInserter_timings_banks_3_active_counter <= (bubbleInserter_timings_banks_3_active_counter - 3'b001); + end + if(bubbleInserter_cmd_valid) begin + case(bubbleInserter_cmd_payload_task) + SdramCtrlBackendTask_MODE : begin + if(bubbleInserter_cmd_ready) begin + if(when_SdramCtrl_l265) begin + bubbleInserter_timings_banks_0_active_counter <= 3'b001; + end + if(when_SdramCtrl_l265_1) begin + bubbleInserter_timings_banks_1_active_counter <= 3'b001; + end + if(when_SdramCtrl_l265_2) begin + bubbleInserter_timings_banks_2_active_counter <= 3'b001; + end + if(when_SdramCtrl_l265_3) begin + bubbleInserter_timings_banks_3_active_counter <= 3'b001; + end + end + end + SdramCtrlBackendTask_PRECHARGE_ALL : begin + if(bubbleInserter_cmd_ready) begin + if(when_SdramCtrl_l265_4) begin + bubbleInserter_timings_banks_0_active_counter <= 3'b001; + end + end + end + SdramCtrlBackendTask_PRECHARGE_SINGLE : begin + if(bubbleInserter_cmd_ready) begin + if(when_Utils_l1017) begin + if(when_SdramCtrl_l265_5) begin + bubbleInserter_timings_banks_0_active_counter <= 3'b001; + end + end + if(when_Utils_l1017_1) begin + if(when_SdramCtrl_l265_6) begin + bubbleInserter_timings_banks_1_active_counter <= 3'b001; + end + end + if(when_Utils_l1017_2) begin + if(when_SdramCtrl_l265_7) begin + bubbleInserter_timings_banks_2_active_counter <= 3'b001; + end + end + if(when_Utils_l1017_3) begin + if(when_SdramCtrl_l265_8) begin + bubbleInserter_timings_banks_3_active_counter <= 3'b001; + end + end + end + end + SdramCtrlBackendTask_REFRESH : begin + if(bubbleInserter_cmd_ready) begin + if(when_SdramCtrl_l265_9) begin + bubbleInserter_timings_banks_0_active_counter <= 3'b101; + end + if(when_SdramCtrl_l265_10) begin + bubbleInserter_timings_banks_1_active_counter <= 3'b101; + end + if(when_SdramCtrl_l265_11) begin + bubbleInserter_timings_banks_2_active_counter <= 3'b101; + end + if(when_SdramCtrl_l265_12) begin + bubbleInserter_timings_banks_3_active_counter <= 3'b101; + end + end + end + SdramCtrlBackendTask_ACTIVE : begin + if(bubbleInserter_cmd_ready) begin + if(when_SdramCtrl_l265_13) begin + bubbleInserter_timings_write_counter <= 3'b001; + end + bubbleInserter_timings_read_counter <= 1'b1; + if(when_Utils_l1017_4) begin + if(when_SdramCtrl_l265_14) begin + bubbleInserter_timings_banks_0_precharge_counter <= 3'b100; + end + end + if(when_Utils_l1017_5) begin + if(when_SdramCtrl_l265_15) begin + bubbleInserter_timings_banks_1_precharge_counter <= 3'b100; + end + end + if(when_Utils_l1017_6) begin + if(when_SdramCtrl_l265_16) begin + bubbleInserter_timings_banks_2_precharge_counter <= 3'b100; + end + end + if(when_Utils_l1017_7) begin + if(when_SdramCtrl_l265_17) begin + bubbleInserter_timings_banks_3_precharge_counter <= 3'b100; + end + end + if(when_Utils_l1017_8) begin + if(when_SdramCtrl_l265_18) begin + bubbleInserter_timings_banks_0_active_counter <= 3'b101; + end + end + if(when_Utils_l1017_9) begin + if(when_SdramCtrl_l265_19) begin + bubbleInserter_timings_banks_1_active_counter <= 3'b101; + end + end + if(when_Utils_l1017_10) begin + if(when_SdramCtrl_l265_20) begin + bubbleInserter_timings_banks_2_active_counter <= 3'b101; + end + end + if(when_Utils_l1017_11) begin + if(when_SdramCtrl_l265_21) begin + bubbleInserter_timings_banks_3_active_counter <= 3'b101; + end + end + end + end + SdramCtrlBackendTask_READ : begin + if(bubbleInserter_cmd_ready) begin + if(when_SdramCtrl_l265_22) begin + bubbleInserter_timings_write_counter <= 3'b100; + end + end + end + default : begin + if(bubbleInserter_cmd_ready) begin + if(when_Utils_l1017_12) begin + if(when_SdramCtrl_l265_23) begin + bubbleInserter_timings_banks_0_precharge_counter <= 3'b001; + end + end + if(when_Utils_l1017_13) begin + if(when_SdramCtrl_l265_24) begin + bubbleInserter_timings_banks_1_precharge_counter <= 3'b001; + end + end + if(when_Utils_l1017_14) begin + if(when_SdramCtrl_l265_25) begin + bubbleInserter_timings_banks_2_precharge_counter <= 3'b001; + end + end + if(when_Utils_l1017_15) begin + if(when_SdramCtrl_l265_26) begin + bubbleInserter_timings_banks_3_precharge_counter <= 3'b001; + end + end + end + end + endcase + end + if(chip_remoteCke) begin + _zz_chip_readHistory_1 <= _zz_chip_readHistory_0; + end + if(chip_remoteCke) begin + _zz_chip_readHistory_2 <= _zz_chip_readHistory_1; + end + if(chip_remoteCke) begin + _zz_chip_readHistory_3 <= _zz_chip_readHistory_2; + end + if(chip_remoteCke) begin + _zz_chip_readHistory_4 <= _zz_chip_readHistory_3; + end + if(chip_remoteCke) begin + _zz_chip_readHistory_5 <= _zz_chip_readHistory_4; + end + chip_sdramCkeInternal <= chip_sdramCkeNext; + chip_sdramCkeInternal_regNext <= chip_sdramCkeInternal; + end + end + + always @(posedge clk) begin + case(frontend_state) + SdramCtrlFrontendState_BOOT_PRECHARGE : begin + end + SdramCtrlFrontendState_BOOT_REFRESH : begin + end + SdramCtrlFrontendState_BOOT_MODE : begin + end + default : begin + if(!refresh_pending) begin + if(io_bus_cmd_valid) begin + if(!when_SdramCtrl_l224) begin + if(when_SdramCtrl_l229) begin + if(_zz_2) begin + frontend_banks_0_row <= frontend_address_row; + end + if(_zz_3) begin + frontend_banks_1_row <= frontend_address_row; + end + if(_zz_4) begin + frontend_banks_2_row <= frontend_address_row; + end + if(_zz_5) begin + frontend_banks_3_row <= frontend_address_row; + end + end + end + end + end + end + endcase + if(frontend_rsp_ready) begin + frontend_rsp_rData_task <= frontend_rsp_payload_task; + frontend_rsp_rData_bank <= frontend_rsp_payload_bank; + frontend_rsp_rData_rowColumn <= frontend_rsp_payload_rowColumn; + frontend_rsp_rData_data <= frontend_rsp_payload_data; + frontend_rsp_rData_mask <= frontend_rsp_payload_mask; + frontend_rsp_rData_context <= frontend_rsp_payload_context; + end + if(chip_remoteCke) begin + chip_cmd_payload_context_delay_1 <= chip_cmd_payload_context; + end + if(chip_remoteCke) begin + chip_cmd_payload_context_delay_2 <= chip_cmd_payload_context_delay_1; + end + if(chip_remoteCke) begin + chip_cmd_payload_context_delay_3 <= chip_cmd_payload_context_delay_2; + end + if(chip_remoteCke) begin + chip_cmd_payload_context_delay_4 <= chip_cmd_payload_context_delay_3; + end + if(chip_remoteCke) begin + chip_contextDelayed <= chip_cmd_payload_context_delay_4; + end + chip_sdram_CKE <= chip_sdramCkeNext; + if(chip_remoteCke) begin + chip_sdram_DQ_read <= io_sdram_DQ_read; + chip_sdram_CSn <= 1'b0; + chip_sdram_RASn <= 1'b1; + chip_sdram_CASn <= 1'b1; + chip_sdram_WEn <= 1'b1; + chip_sdram_DQ_write <= chip_cmd_payload_data; + chip_sdram_DQ_writeEnable <= 16'h0000; + chip_sdram_DQM[0] <= _zz_chip_sdram_DQM; + chip_sdram_DQM[1] <= _zz_chip_sdram_DQM; + if(chip_cmd_valid) begin + case(chip_cmd_payload_task) + SdramCtrlBackendTask_PRECHARGE_ALL : begin + chip_sdram_ADDR[10] <= 1'b1; + chip_sdram_CSn <= 1'b0; + chip_sdram_RASn <= 1'b0; + chip_sdram_CASn <= 1'b1; + chip_sdram_WEn <= 1'b0; + end + SdramCtrlBackendTask_REFRESH : begin + chip_sdram_CSn <= 1'b0; + chip_sdram_RASn <= 1'b0; + chip_sdram_CASn <= 1'b0; + chip_sdram_WEn <= 1'b1; + end + SdramCtrlBackendTask_MODE : begin + chip_sdram_ADDR <= 13'h0000; + chip_sdram_ADDR[2 : 0] <= 3'b000; + chip_sdram_ADDR[3] <= 1'b0; + chip_sdram_ADDR[6 : 4] <= 3'b011; + chip_sdram_ADDR[8 : 7] <= 2'b00; + chip_sdram_ADDR[9] <= 1'b0; + chip_sdram_BA <= 2'b00; + chip_sdram_CSn <= 1'b0; + chip_sdram_RASn <= 1'b0; + chip_sdram_CASn <= 1'b0; + chip_sdram_WEn <= 1'b0; + end + SdramCtrlBackendTask_ACTIVE : begin + chip_sdram_ADDR <= chip_cmd_payload_rowColumn; + chip_sdram_BA <= chip_cmd_payload_bank; + chip_sdram_CSn <= 1'b0; + chip_sdram_RASn <= 1'b0; + chip_sdram_CASn <= 1'b1; + chip_sdram_WEn <= 1'b1; + end + SdramCtrlBackendTask_WRITE : begin + chip_sdram_ADDR <= chip_cmd_payload_rowColumn; + chip_sdram_ADDR[10] <= 1'b0; + chip_sdram_DQ_writeEnable <= 16'hffff; + chip_sdram_DQ_write <= chip_cmd_payload_data; + chip_sdram_DQM <= (~ chip_cmd_payload_mask); + chip_sdram_BA <= chip_cmd_payload_bank; + chip_sdram_CSn <= 1'b0; + chip_sdram_RASn <= 1'b1; + chip_sdram_CASn <= 1'b0; + chip_sdram_WEn <= 1'b0; + end + SdramCtrlBackendTask_READ : begin + chip_sdram_ADDR <= chip_cmd_payload_rowColumn; + chip_sdram_ADDR[10] <= 1'b0; + chip_sdram_BA <= chip_cmd_payload_bank; + chip_sdram_CSn <= 1'b0; + chip_sdram_RASn <= 1'b1; + chip_sdram_CASn <= 1'b0; + chip_sdram_WEn <= 1'b1; + end + default : begin + chip_sdram_BA <= chip_cmd_payload_bank; + chip_sdram_ADDR[10] <= 1'b0; + chip_sdram_CSn <= 1'b0; + chip_sdram_RASn <= 1'b0; + chip_sdram_CASn <= 1'b1; + chip_sdram_WEn <= 1'b0; + end + endcase + end + end + end + + +endmodule + +module StreamFifoLowLatency ( + input wire io_push_valid, + output wire io_push_ready, + input wire [15:0] io_push_payload_data, + input wire io_push_payload_context, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [15:0] io_pop_payload_data, + output wire io_pop_payload_context, + input wire io_flush, + output wire [1:0] io_occupancy, + output wire [1:0] io_availability, + input wire clk, + input wire reset +); + + wire fifo_io_push_ready; + wire fifo_io_pop_valid; + wire [15:0] fifo_io_pop_payload_data; + wire fifo_io_pop_payload_context; + wire [1:0] fifo_io_occupancy; + wire [1:0] fifo_io_availability; + + StreamFifo fifo ( + .io_push_valid (io_push_valid ), //i + .io_push_ready (fifo_io_push_ready ), //o + .io_push_payload_data (io_push_payload_data[15:0] ), //i + .io_push_payload_context (io_push_payload_context ), //i + .io_pop_valid (fifo_io_pop_valid ), //o + .io_pop_ready (io_pop_ready ), //i + .io_pop_payload_data (fifo_io_pop_payload_data[15:0]), //o + .io_pop_payload_context (fifo_io_pop_payload_context ), //o + .io_flush (io_flush ), //i + .io_occupancy (fifo_io_occupancy[1:0] ), //o + .io_availability (fifo_io_availability[1:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_push_ready = fifo_io_push_ready; + assign io_pop_valid = fifo_io_pop_valid; + assign io_pop_payload_data = fifo_io_pop_payload_data; + assign io_pop_payload_context = fifo_io_pop_payload_context; + assign io_occupancy = fifo_io_occupancy; + assign io_availability = fifo_io_availability; + +endmodule + +module StreamFifo ( + input wire io_push_valid, + output wire io_push_ready, + input wire [15:0] io_push_payload_data, + input wire io_push_payload_context, + output reg io_pop_valid, + input wire io_pop_ready, + output reg [15:0] io_pop_payload_data, + output reg io_pop_payload_context, + input wire io_flush, + output wire [1:0] io_occupancy, + output wire [1:0] io_availability, + input wire clk, + input wire reset +); + + wire [16:0] _zz_logic_ram_port1; + wire [16:0] _zz_logic_ram_port; + reg _zz_1; + reg logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [1:0] logic_ptr_push; + reg [1:0] logic_ptr_pop; + wire [1:0] logic_ptr_occupancy; + wire [1:0] logic_ptr_popOnIo; + wire when_Stream_l1205; + reg logic_ptr_wentUp; + wire io_push_fire; + wire logic_push_onRam_write_valid; + wire [0:0] logic_push_onRam_write_payload_address; + wire [15:0] logic_push_onRam_write_payload_data_data; + wire logic_push_onRam_write_payload_data_context; + wire logic_pop_addressGen_valid; + wire logic_pop_addressGen_ready; + wire [0:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire [15:0] logic_pop_async_readed_data; + wire logic_pop_async_readed_context; + wire [16:0] _zz_logic_pop_async_readed_data; + wire logic_pop_addressGen_translated_valid; + wire logic_pop_addressGen_translated_ready; + wire [15:0] logic_pop_addressGen_translated_payload_data; + wire logic_pop_addressGen_translated_payload_context; + (* ram_style = "distributed" *) reg [16:0] logic_ram [0:1]; + + assign _zz_logic_ram_port = {logic_push_onRam_write_payload_data_context,logic_push_onRam_write_payload_data_data}; + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= _zz_logic_ram_port; + end + end + + assign _zz_logic_ram_port1 = logic_ram[logic_pop_addressGen_payload]; + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1205 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 2'b10) == 2'b00); + assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); + assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); + assign io_push_ready = (! logic_ptr_full); + assign io_push_fire = (io_push_valid && io_push_ready); + always @(*) begin + logic_ptr_doPush = io_push_fire; + if(logic_ptr_empty) begin + if(io_pop_ready) begin + logic_ptr_doPush = 1'b0; + end + end + end + + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push[0:0]; + assign logic_push_onRam_write_payload_data_data = io_push_payload_data; + assign logic_push_onRam_write_payload_data_context = io_push_payload_context; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop[0:0]; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + assign _zz_logic_pop_async_readed_data = _zz_logic_ram_port1; + assign logic_pop_async_readed_data = _zz_logic_pop_async_readed_data[15 : 0]; + assign logic_pop_async_readed_context = _zz_logic_pop_async_readed_data[16]; + assign logic_pop_addressGen_translated_valid = logic_pop_addressGen_valid; + assign logic_pop_addressGen_ready = logic_pop_addressGen_translated_ready; + assign logic_pop_addressGen_translated_payload_data = logic_pop_async_readed_data; + assign logic_pop_addressGen_translated_payload_context = logic_pop_async_readed_context; + always @(*) begin + io_pop_valid = logic_pop_addressGen_translated_valid; + if(logic_ptr_empty) begin + io_pop_valid = io_push_valid; + end + end + + assign logic_pop_addressGen_translated_ready = io_pop_ready; + always @(*) begin + io_pop_payload_data = logic_pop_addressGen_translated_payload_data; + if(logic_ptr_empty) begin + io_pop_payload_data = io_push_payload_data; + end + end + + always @(*) begin + io_pop_payload_context = logic_pop_addressGen_translated_payload_context; + if(logic_ptr_empty) begin + io_pop_payload_context = io_push_payload_context; + end + end + + assign logic_ptr_popOnIo = logic_ptr_pop; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (2'b10 - logic_ptr_occupancy); + always @(posedge clk or posedge reset) begin + if(reset) begin + logic_ptr_push <= 2'b00; + logic_ptr_pop <= 2'b00; + logic_ptr_wentUp <= 1'b0; + end else begin + if(when_Stream_l1205) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 2'b01); + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 2'b01); + end + if(io_flush) begin + logic_ptr_push <= 2'b00; + logic_ptr_pop <= 2'b00; + end + end + end + + +endmodule diff --git a/SDRAM.stp b/SDRAM.stp new file mode 100644 index 0000000..2835005 --- /dev/null +++ b/SDRAM.stp @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/Sdram_Tester.v b/Sdram_Tester.v new file mode 100644 index 0000000..8e4464f --- /dev/null +++ b/Sdram_Tester.v @@ -0,0 +1,132 @@ +`timescale 1ns/1ps + +module Sdram_Tester #( + parameter TEST_LENGTH = 24'd1048576 +)( + input wire clk, + input wire rst_n, + + // --- 连接到 SDRAM 控制器的用户接口 --- + output reg cmd_valid, + input wire cmd_ready, + output reg is_write, + output reg [23:0] address, + output wire [15:0] write_data, + + input wire rsp_valid, + input wire [15:0] rsp_data, + + // --- 外部 LED 状态指示灯 --- + output reg test_pass, // 绿色 LED，成功后闪烁 + output reg test_fail // 红色 LED，发生错误时常亮 +); + + // ========================================== + // 状态机定义 + // ========================================== + localparam S_INIT = 3'd0; // 等待 SDRAM 初始化 + localparam S_WRITE = 3'd1; // 发起单次写命令 + localparam S_READ = 3'd2; // 发起单次读命令 (交替操作) + localparam S_WAIT_RSP = 3'd3; // 等待读响应并比对 + localparam S_DONE = 3'd4; // 测试成功完成 + localparam S_ERROR = 3'd5; // 数据校验错误 + + reg [2:0] state; + reg [15:0] init_cnt; // 用于上电延时计数 + reg [23:0] test_addr; // 当前正在测试的地址 + + // 新增：用于控制 LED 闪烁的 26 位计数器 + reg [25:0] blink_cnt; + + // ========================================== + // 测试数据生成器 + // ========================================== + // 地址低16位 异或 0x5A5A，保证每个地址的数据唯一且具有翻转特性 + wire [15:0] expected_data = test_addr[15:0] ^ 16'h5A5A; + assign write_data = expected_data; + + // ========================================== + // 主状态机控制逻辑 + // ========================================== + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + state <= S_INIT; + init_cnt <= 16'd0; + test_addr <= 24'd0; + blink_cnt <= 26'd0; // 复位闪烁计数器 + cmd_valid <= 1'b0; + is_write <= 1'b0; + address <= 24'd0; + test_pass <= 1'b0; + test_fail <= 1'b0; + end else begin + case (state) + // 1. 等待初始化 (200us @ 100MHz) + S_INIT: begin + if (init_cnt < 16'd20000) begin + init_cnt <= init_cnt + 1'b1; + end else begin + state <= S_WRITE; + end + end + + // 2. 写操作 + S_WRITE: begin + cmd_valid <= 1'b1; + is_write <= 1'b1; + address <= test_addr; + + if (cmd_valid && cmd_ready) begin + cmd_valid <= 1'b0; + state <= S_READ; + end + end + + // 3. 读操作 + S_READ: begin + cmd_valid <= 1'b1; + is_write <= 1'b0; + address <= test_addr; + + if (cmd_valid && cmd_ready) begin + cmd_valid <= 1'b0; + state <= S_WAIT_RSP; + end + end + + // 4. 数据比对 + S_WAIT_RSP: begin + if (rsp_valid) begin + if (rsp_data == expected_data) begin + if (test_addr == TEST_LENGTH - 1) begin + state <= S_DONE; + end else begin + test_addr <= test_addr + 2'b11; + state <= S_WRITE; + end + end else begin + state <= S_ERROR; + end + end + end + + // 5. 测试通过：LED 闪烁逻辑 + S_DONE: begin + // 计数器不断累加 + blink_cnt <= blink_cnt + 1'b1; + test_pass <= blink_cnt[25]; + test_fail <= 1'b0; + end + + // 6. 测试失败：红灯常亮 + S_ERROR: begin + test_pass <= 1'b0; + test_fail <= 1'b1; + end + + default: state <= S_INIT; + endcase + end + end + +endmodule \ No newline at end of file diff --git a/Top_Project.v b/Top_Project.v new file mode 100644 index 0000000..13778c6 --- /dev/null +++ b/Top_Project.v @@ -0,0 +1,143 @@ +`timescale 1ns/1ps + +module Top_Project ( + // ========================================== + // 1. 系统全局时钟与复位输入 + // ========================================== + input wire sys_clk_50m, // 开发板上的 50MHz 晶振输入 + input wire sys_rst_n, // 开发板上的复位按键 (低电平有效，按下为0) + + // ========================================== + // 2. 外部 SDRAM 物理芯片接口 (匹配 W9825G6JH-6) + // ========================================== + output wire [12:0] sdram_ADDR, // 13位行地址 / 9位列地址复用 + output wire [1:0] sdram_BA, // 2位 Bank 地址 + inout wire [15:0] sdram_DQ, // 16位数据总线 (必须是 inout 双向类型) + output wire [1:0] sdram_DQM, // 数据掩码 + output wire sdram_CASn, // 列选通 (低有效) + output wire sdram_CKE, // 时钟使能 + output wire sdram_CSn, // 片选 (低有效) + output wire sdram_RASn, // 行选通 (低有效) + output wire sdram_WEn, // 写使能 (低有效) + output wire sdram_CLK, // 输出给 SDRAM 芯片的时钟引脚 (带相位偏移) + + // ========================================== + // 3. 测试状态指示灯 (新增) + // ========================================== + output wire led_test_pass, // 测试通过指示灯 (建议接绿色 LED) + output wire led_test_fail // 测试失败指示灯 (建议接红色 LED) +); + + // ========================================== + // 内部信号声明 + // ========================================== + wire clk_100m; // PLL 输出的 100MHz (0度相位，给 FPGA 内部逻辑用) + wire clk_100m_shift; // PLL 输出的 100MHz (-90度相位，给 SDRAM 芯片用) + wire pll_locked; // PLL 锁定指示信号 (高电平表示时钟已稳定输出) + + wire [15:0] sdram_DQ_read; // 从双向引脚分离出的读数据 + wire [15:0] sdram_DQ_write; // 准备输出到双向引脚的写数据 + wire [15:0] sdram_DQ_writeEnable; // 控制总线方向的写使能信号 + + // --- 新增：用户逻辑交互总线连线 --- + wire user_cmd_valid; + wire user_cmd_ready; + wire user_is_write; + wire [23:0] user_address; + wire [15:0] user_write_data; + wire user_rsp_valid; + wire [15:0] user_rsp_data; + + // ========================================== + // 模块 1：例化系统 PLL IP 核 (sys_pll) + // ========================================== + sys_pll u_sys_pll ( + // ALTPLL 的 areset 是高电平有效。 + // 因为板载按键 sys_rst_n 是低电平有效，所以这里必须加非逻辑 '~' + .areset (~sys_rst_n), + .inclk0 (sys_clk_50m), + .c0 (clk_100m), // 内部 100MHz 时钟 + .c1 (clk_100m_shift),// 偏移 100MHz 时钟 + .locked (pll_locked) + ); + + // 将带有 -90 度相位偏移的时钟直接连到顶层输出引脚，送给 SDRAM 物理芯片 + assign sdram_CLK = clk_100m_shift; + + // ========================================== + // 模块 2：复位信号反相与同步处理 + // ========================================== + // SpinalHDL 生成的 MyCustomSdramTop 是【高电平复位】的。 + // 我们在此生成一个全局的【高电平有效】复位信号 system_reset。 + wire system_reset; + assign system_reset = (~sys_rst_n) | (~pll_locked); + + // ========================================== + // 模块 3：处理 SDRAM 双向数据总线 (inout 三态门) + // ========================================== + // 读取通道：直接将外部管脚状态输入给控制器 + assign sdram_DQ_read = sdram_DQ; + + // 写入通道：通过三态门控制 + // 当控制器拉高写使能 (16'hFFFF) 时，将写数据推送到总线上。 + assign sdram_DQ = (sdram_DQ_writeEnable == 16'hFFFF) ? sdram_DQ_write : 16'hZZZZ; + + // ========================================== + // 模块 4：例化由 SpinalHDL 生成的 SDRAM 控制器 + // ========================================== + MyCustomSdramTop u_sdram_ctrl ( + // --- 时钟与复位 --- + .clk (clk_100m), // 接入稳定的 100MHz 内部时钟 + .reset (system_reset), // 接入经过处理的高有效复位信号 + + // --- 连接到底层的 SDRAM 物理接口信号 --- + .io_sdram_ADDR (sdram_ADDR), + .io_sdram_BA (sdram_BA), + .io_sdram_DQ_read (sdram_DQ_read), + .io_sdram_DQ_write (sdram_DQ_write), + .io_sdram_DQ_writeEnable (sdram_DQ_writeEnable), + .io_sdram_DQM (sdram_DQM), + .io_sdram_CASn (sdram_CASn), + .io_sdram_CKE (sdram_CKE), + .io_sdram_CSn (sdram_CSn), + .io_sdram_RASn (sdram_RASn), + .io_sdram_WEn (sdram_WEn), + + // --- 连接到测试模块的用户逻辑接口 --- + .io_userCmdValid (user_cmd_valid), + .io_userCmdReady (user_cmd_ready), + .io_userIsWrite (user_is_write), + .io_userAddress (user_address), + .io_userWriteData (user_write_data), + .io_userWriteMask (2'b11), // 写数据掩码 (2'b00表示16位全部写入，不屏蔽) + + .io_userRspValid (user_rsp_valid), + .io_userRspData (user_rsp_data) + ); + + // ========================================== + // 模块 5：例化读写校验测试模块 (新增) + // ========================================== + Sdram_Tester #( + .TEST_LENGTH(24'd4096) // 测试的地址长度，这里设置为测试前 4096 个地址 + ) u_tester ( + .clk (clk_100m), + // 注意：Tester 内部是下降沿复位 (低有效)，所以需要将高有效的 system_reset 取反 + .rst_n (~system_reset), + + // --- 挂载到 SDRAM 用户总线 --- + .cmd_valid (user_cmd_valid), + .cmd_ready (user_cmd_ready), + .is_write (user_is_write), + .address (user_address), + .write_data (user_write_data), + + .rsp_valid (user_rsp_valid), + .rsp_data (user_rsp_data), + + // --- 连接到顶层外部引脚 --- + .test_pass (led_test_pass), + .test_fail (led_test_fail) + ); + +endmodule \ No newline at end of file diff --git a/ip_core/sys_pll.ppf b/ip_core/sys_pll.ppf new file mode 100644 index 0000000..779646e --- /dev/null +++ b/ip_core/sys_pll.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/ip_core/sys_pll.qip b/ip_core/sys_pll.qip new file mode 100644 index 0000000..05a487a --- /dev/null +++ b/ip_core/sys_pll.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sys_pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sys_pll_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sys_pll.ppf"] diff --git a/ip_core/sys_pll.v b/ip_core/sys_pll.v new file mode 100644 index 0000000..513730d --- /dev/null +++ b/ip_core/sys_pll.v @@ -0,0 +1,348 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: sys_pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.0 Build 625 09/12/2018 SJ Standard Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module sys_pll ( + areset, + inclk0, + c0, + c1, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [0:0] sub_wire2 = 1'h0; + wire [4:0] sub_wire3; + wire sub_wire6; + wire sub_wire0 = inclk0; + wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; + wire [1:1] sub_wire5 = sub_wire3[1:1]; + wire [0:0] sub_wire4 = sub_wire3[0:0]; + wire c0 = sub_wire4; + wire c1 = sub_wire5; + wire locked = sub_wire6; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire1), + .clk (sub_wire3), + .locked (sub_wire6), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 1, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 2, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 1, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 2, + altpll_component.clk1_phase_shift = "-2500", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Cyclone IV E", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=sys_pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-90.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sys_pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2500" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/ip_core/sys_pll_bb.v b/ip_core/sys_pll_bb.v new file mode 100644 index 0000000..c583ace --- /dev/null +++ b/ip_core/sys_pll_bb.v @@ -0,0 +1,232 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: sys_pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.0 Build 625 09/12/2018 SJ Standard Edition +// ************************************************************ + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + +module sys_pll ( + areset, + inclk0, + c0, + c1, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-90.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sys_pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2500" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/spinalSdram.qpf b/spinalSdram.qpf new file mode 100644 index 0000000..c3d84b6 --- /dev/null +++ b/spinalSdram.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +# Date created = 15:18:00 April 07, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.1" +DATE = "15:18:00 April 07, 2026" + +# Revisions + +PROJECT_REVISION = "spinalSdram" diff --git a/spinalSdram.qsf b/spinalSdram.qsf new file mode 100644 index 0000000..77c0364 --- /dev/null +++ b/spinalSdram.qsf @@ -0,0 +1,96 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +# Date created = 15:18:00 April 07, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# spinalSdram_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV GX" +set_global_assignment -name DEVICE EP4CGX150DF27I7 +set_global_assignment -name TOP_LEVEL_ENTITY Top_Project +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:18:00 APRIL 07, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +# ======================================================== +# 系统时钟与复位 (注意：你提供的信息中缺失了这两个，请根据你的开发板原理图补全) +# ======================================================== + +# ======================================================== +# SDRAM 时钟与控制信号 +# ======================================================== + +# ======================================================== +# SDRAM Bank 与 数据掩码 (DQM) +# ======================================================== + +# ======================================================== +# SDRAM 行/列地址总线 (13位) +# ======================================================== + +# ======================================================== +# SDRAM 数据总线 (16位) +# ======================================================== +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name VERILOG_FILE Sdram_Tester.v +set_global_assignment -name VERILOG_FILE Top_Project.v +set_global_assignment -name VERILOG_FILE MyCustomSdramTop.v +set_global_assignment -name QIP_FILE ip_core/sys_pll.qip + +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE SDRAM.stp +set_global_assignment -name SIGNALTAP_FILE SDRAM.stp +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name SLD_FILE db/SDRAM_auto_stripped.stp \ No newline at end of file