1475 lines
67 KiB
Verilog
1475 lines
67 KiB
Verilog
// Generator : SpinalHDL v1.10.1 git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43
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// Component : MyCustomSdramTop
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`timescale 1ns/1ps
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module MyCustomSdramTop (
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output wire [12:0] io_sdram_ADDR,
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output wire [1:0] io_sdram_BA,
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input wire [15:0] io_sdram_DQ_read,
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output wire [15:0] io_sdram_DQ_write,
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output wire [15:0] io_sdram_DQ_writeEnable,
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output wire [1:0] io_sdram_DQM,
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output wire io_sdram_CASn,
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output wire io_sdram_CKE,
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output wire io_sdram_CSn,
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output wire io_sdram_RASn,
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output wire io_sdram_WEn,
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input wire io_userCmdValid,
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output wire io_userCmdReady,
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input wire io_userIsWrite,
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input wire [23:0] io_userAddress,
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input wire [15:0] io_userWriteData,
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input wire [1:0] io_userWriteMask,
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output wire io_userRspValid,
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output wire [15:0] io_userRspData,
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input wire clk,
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input wire reset
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);
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wire sdramCtrl_1_io_bus_cmd_payload_context;
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wire sdramCtrl_1_io_bus_rsp_ready;
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wire sdramCtrl_1_io_bus_cmd_ready;
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wire sdramCtrl_1_io_bus_rsp_valid;
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wire [15:0] sdramCtrl_1_io_bus_rsp_payload_data;
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wire sdramCtrl_1_io_bus_rsp_payload_context;
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wire [12:0] sdramCtrl_1_io_sdram_ADDR;
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wire [1:0] sdramCtrl_1_io_sdram_BA;
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wire sdramCtrl_1_io_sdram_CASn;
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wire sdramCtrl_1_io_sdram_CKE;
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wire sdramCtrl_1_io_sdram_CSn;
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wire [1:0] sdramCtrl_1_io_sdram_DQM;
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wire sdramCtrl_1_io_sdram_RASn;
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wire sdramCtrl_1_io_sdram_WEn;
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wire [15:0] sdramCtrl_1_io_sdram_DQ_write;
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wire [15:0] sdramCtrl_1_io_sdram_DQ_writeEnable;
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SdramCtrl sdramCtrl_1 (
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.io_bus_cmd_valid (io_userCmdValid ), //i
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.io_bus_cmd_ready (sdramCtrl_1_io_bus_cmd_ready ), //o
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.io_bus_cmd_payload_address (io_userAddress[23:0] ), //i
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.io_bus_cmd_payload_write (io_userIsWrite ), //i
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.io_bus_cmd_payload_data (io_userWriteData[15:0] ), //i
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.io_bus_cmd_payload_mask (io_userWriteMask[1:0] ), //i
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.io_bus_cmd_payload_context (sdramCtrl_1_io_bus_cmd_payload_context ), //i
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.io_bus_rsp_valid (sdramCtrl_1_io_bus_rsp_valid ), //o
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.io_bus_rsp_ready (sdramCtrl_1_io_bus_rsp_ready ), //i
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.io_bus_rsp_payload_data (sdramCtrl_1_io_bus_rsp_payload_data[15:0]), //o
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.io_bus_rsp_payload_context (sdramCtrl_1_io_bus_rsp_payload_context ), //o
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.io_sdram_ADDR (sdramCtrl_1_io_sdram_ADDR[12:0] ), //o
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.io_sdram_BA (sdramCtrl_1_io_sdram_BA[1:0] ), //o
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.io_sdram_DQ_read (io_sdram_DQ_read[15:0] ), //i
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.io_sdram_DQ_write (sdramCtrl_1_io_sdram_DQ_write[15:0] ), //o
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.io_sdram_DQ_writeEnable (sdramCtrl_1_io_sdram_DQ_writeEnable[15:0]), //o
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.io_sdram_DQM (sdramCtrl_1_io_sdram_DQM[1:0] ), //o
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.io_sdram_CASn (sdramCtrl_1_io_sdram_CASn ), //o
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.io_sdram_CKE (sdramCtrl_1_io_sdram_CKE ), //o
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.io_sdram_CSn (sdramCtrl_1_io_sdram_CSn ), //o
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.io_sdram_RASn (sdramCtrl_1_io_sdram_RASn ), //o
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.io_sdram_WEn (sdramCtrl_1_io_sdram_WEn ), //o
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.clk (clk ), //i
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.reset (reset ) //i
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);
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assign io_sdram_ADDR = sdramCtrl_1_io_sdram_ADDR;
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assign io_sdram_BA = sdramCtrl_1_io_sdram_BA;
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assign io_sdram_DQ_write = sdramCtrl_1_io_sdram_DQ_write;
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assign io_sdram_DQ_writeEnable = sdramCtrl_1_io_sdram_DQ_writeEnable;
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assign io_sdram_DQM = sdramCtrl_1_io_sdram_DQM;
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assign io_sdram_CASn = sdramCtrl_1_io_sdram_CASn;
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assign io_sdram_CKE = sdramCtrl_1_io_sdram_CKE;
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assign io_sdram_CSn = sdramCtrl_1_io_sdram_CSn;
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assign io_sdram_RASn = sdramCtrl_1_io_sdram_RASn;
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assign io_sdram_WEn = sdramCtrl_1_io_sdram_WEn;
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assign io_userCmdReady = sdramCtrl_1_io_bus_cmd_ready;
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assign sdramCtrl_1_io_bus_cmd_payload_context = 1'b0;
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assign io_userRspValid = sdramCtrl_1_io_bus_rsp_valid;
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assign io_userRspData = sdramCtrl_1_io_bus_rsp_payload_data;
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assign sdramCtrl_1_io_bus_rsp_ready = 1'b1;
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endmodule
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module SdramCtrl (
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input wire io_bus_cmd_valid,
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output reg io_bus_cmd_ready,
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input wire [23:0] io_bus_cmd_payload_address,
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input wire io_bus_cmd_payload_write,
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input wire [15:0] io_bus_cmd_payload_data,
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input wire [1:0] io_bus_cmd_payload_mask,
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input wire io_bus_cmd_payload_context,
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output wire io_bus_rsp_valid,
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input wire io_bus_rsp_ready,
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output wire [15:0] io_bus_rsp_payload_data,
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output wire io_bus_rsp_payload_context,
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output wire [12:0] io_sdram_ADDR,
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output wire [1:0] io_sdram_BA,
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input wire [15:0] io_sdram_DQ_read,
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output wire [15:0] io_sdram_DQ_write,
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output wire [15:0] io_sdram_DQ_writeEnable,
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output wire [1:0] io_sdram_DQM,
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output wire io_sdram_CASn,
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output wire io_sdram_CKE,
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output wire io_sdram_CSn,
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output wire io_sdram_RASn,
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output wire io_sdram_WEn,
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input wire clk,
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input wire reset
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);
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localparam SdramCtrlBackendTask_MODE = 3'd0;
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localparam SdramCtrlBackendTask_PRECHARGE_ALL = 3'd1;
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localparam SdramCtrlBackendTask_PRECHARGE_SINGLE = 3'd2;
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localparam SdramCtrlBackendTask_REFRESH = 3'd3;
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localparam SdramCtrlBackendTask_ACTIVE = 3'd4;
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localparam SdramCtrlBackendTask_READ = 3'd5;
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localparam SdramCtrlBackendTask_WRITE = 3'd6;
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localparam SdramCtrlFrontendState_BOOT_PRECHARGE = 2'd0;
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localparam SdramCtrlFrontendState_BOOT_REFRESH = 2'd1;
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localparam SdramCtrlFrontendState_BOOT_MODE = 2'd2;
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localparam SdramCtrlFrontendState_RUN = 2'd3;
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wire chip_backupIn_fifo_io_flush;
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wire chip_backupIn_fifo_io_push_ready;
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wire chip_backupIn_fifo_io_pop_valid;
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wire [15:0] chip_backupIn_fifo_io_pop_payload_data;
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wire chip_backupIn_fifo_io_pop_payload_context;
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wire [1:0] chip_backupIn_fifo_io_occupancy;
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wire [1:0] chip_backupIn_fifo_io_availability;
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wire [9:0] _zz_refresh_counter_valueNext;
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wire [0:0] _zz_refresh_counter_valueNext_1;
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wire [2:0] _zz_frontend_bootRefreshCounter_valueNext;
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wire [0:0] _zz_frontend_bootRefreshCounter_valueNext_1;
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reg _zz__zz_when_SdramCtrl_l224;
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reg [12:0] _zz_when_SdramCtrl_l224_1;
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reg _zz_bubbleInserter_insertBubble;
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reg _zz_bubbleInserter_insertBubble_1;
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wire refresh_counter_willIncrement;
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wire refresh_counter_willClear;
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reg [9:0] refresh_counter_valueNext;
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reg [9:0] refresh_counter_value;
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wire refresh_counter_willOverflowIfInc;
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wire refresh_counter_willOverflow;
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reg refresh_pending;
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reg [14:0] powerup_counter;
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reg powerup_done;
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wire when_SdramCtrl_l146;
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wire [14:0] _zz_when_SdramCtrl_l148;
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wire when_SdramCtrl_l148;
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reg frontend_banks_0_active;
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reg [12:0] frontend_banks_0_row;
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reg frontend_banks_1_active;
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reg [12:0] frontend_banks_1_row;
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reg frontend_banks_2_active;
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reg [12:0] frontend_banks_2_row;
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reg frontend_banks_3_active;
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reg [12:0] frontend_banks_3_row;
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wire [8:0] frontend_address_column;
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wire [1:0] frontend_address_bank;
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wire [12:0] frontend_address_row;
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wire [23:0] _zz_frontend_address_column;
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reg frontend_rsp_valid;
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reg frontend_rsp_ready;
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reg [2:0] frontend_rsp_payload_task;
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wire [1:0] frontend_rsp_payload_bank;
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reg [12:0] frontend_rsp_payload_rowColumn;
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wire [15:0] frontend_rsp_payload_data;
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wire [1:0] frontend_rsp_payload_mask;
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wire frontend_rsp_payload_context;
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reg [1:0] frontend_state;
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reg frontend_bootRefreshCounter_willIncrement;
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wire frontend_bootRefreshCounter_willClear;
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reg [2:0] frontend_bootRefreshCounter_valueNext;
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reg [2:0] frontend_bootRefreshCounter_value;
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wire frontend_bootRefreshCounter_willOverflowIfInc;
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wire frontend_bootRefreshCounter_willOverflow;
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wire when_SdramCtrl_l210;
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wire _zz_when_SdramCtrl_l224;
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wire [3:0] _zz_1;
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wire _zz_2;
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wire _zz_3;
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wire _zz_4;
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wire _zz_5;
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wire when_SdramCtrl_l224;
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wire [2:0] _zz_frontend_rsp_payload_task;
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wire when_SdramCtrl_l229;
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wire bubbleInserter_cmd_valid;
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wire bubbleInserter_cmd_ready;
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wire [2:0] bubbleInserter_cmd_payload_task;
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wire [1:0] bubbleInserter_cmd_payload_bank;
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wire [12:0] bubbleInserter_cmd_payload_rowColumn;
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wire [15:0] bubbleInserter_cmd_payload_data;
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wire [1:0] bubbleInserter_cmd_payload_mask;
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wire bubbleInserter_cmd_payload_context;
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reg frontend_rsp_rValid;
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reg [2:0] frontend_rsp_rData_task;
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reg [1:0] frontend_rsp_rData_bank;
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reg [12:0] frontend_rsp_rData_rowColumn;
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reg [15:0] frontend_rsp_rData_data;
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reg [1:0] frontend_rsp_rData_mask;
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reg frontend_rsp_rData_context;
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wire when_Stream_l369;
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wire bubbleInserter_rsp_valid;
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wire bubbleInserter_rsp_ready;
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wire [2:0] bubbleInserter_rsp_payload_task;
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wire [1:0] bubbleInserter_rsp_payload_bank;
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wire [12:0] bubbleInserter_rsp_payload_rowColumn;
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wire [15:0] bubbleInserter_rsp_payload_data;
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wire [1:0] bubbleInserter_rsp_payload_mask;
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wire bubbleInserter_rsp_payload_context;
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reg bubbleInserter_insertBubble;
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wire _zz_bubbleInserter_cmd_ready;
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wire [2:0] _zz_bubbleInserter_rsp_payload_task;
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reg [0:0] bubbleInserter_timings_read_counter;
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wire bubbleInserter_timings_read_busy;
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wire when_SdramCtrl_l256;
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reg [2:0] bubbleInserter_timings_write_counter;
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wire bubbleInserter_timings_write_busy;
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wire when_SdramCtrl_l256_1;
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reg [2:0] bubbleInserter_timings_banks_0_precharge_counter;
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wire bubbleInserter_timings_banks_0_precharge_busy;
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wire when_SdramCtrl_l256_2;
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reg [2:0] bubbleInserter_timings_banks_0_active_counter;
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wire bubbleInserter_timings_banks_0_active_busy;
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wire when_SdramCtrl_l256_3;
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reg [2:0] bubbleInserter_timings_banks_1_precharge_counter;
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wire bubbleInserter_timings_banks_1_precharge_busy;
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wire when_SdramCtrl_l256_4;
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reg [2:0] bubbleInserter_timings_banks_1_active_counter;
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wire bubbleInserter_timings_banks_1_active_busy;
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wire when_SdramCtrl_l256_5;
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reg [2:0] bubbleInserter_timings_banks_2_precharge_counter;
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wire bubbleInserter_timings_banks_2_precharge_busy;
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wire when_SdramCtrl_l256_6;
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reg [2:0] bubbleInserter_timings_banks_2_active_counter;
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wire bubbleInserter_timings_banks_2_active_busy;
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wire when_SdramCtrl_l256_7;
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reg [2:0] bubbleInserter_timings_banks_3_precharge_counter;
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wire bubbleInserter_timings_banks_3_precharge_busy;
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wire when_SdramCtrl_l256_8;
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reg [2:0] bubbleInserter_timings_banks_3_active_counter;
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wire bubbleInserter_timings_banks_3_active_busy;
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wire when_SdramCtrl_l256_9;
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wire when_SdramCtrl_l265;
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wire when_SdramCtrl_l265_1;
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wire when_SdramCtrl_l265_2;
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wire when_SdramCtrl_l265_3;
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wire when_SdramCtrl_l265_4;
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wire when_Utils_l1017;
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wire when_SdramCtrl_l265_5;
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wire when_Utils_l1017_1;
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wire when_SdramCtrl_l265_6;
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wire when_Utils_l1017_2;
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wire when_SdramCtrl_l265_7;
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wire when_Utils_l1017_3;
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wire when_SdramCtrl_l265_8;
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wire when_SdramCtrl_l265_9;
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wire when_SdramCtrl_l265_10;
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wire when_SdramCtrl_l265_11;
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wire when_SdramCtrl_l265_12;
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wire when_SdramCtrl_l265_13;
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wire when_Utils_l1017_4;
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wire when_SdramCtrl_l265_14;
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wire when_Utils_l1017_5;
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wire when_SdramCtrl_l265_15;
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wire when_Utils_l1017_6;
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wire when_SdramCtrl_l265_16;
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wire when_Utils_l1017_7;
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wire when_SdramCtrl_l265_17;
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wire when_Utils_l1017_8;
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wire when_SdramCtrl_l265_18;
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wire when_Utils_l1017_9;
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wire when_SdramCtrl_l265_19;
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wire when_Utils_l1017_10;
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wire when_SdramCtrl_l265_20;
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wire when_Utils_l1017_11;
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wire when_SdramCtrl_l265_21;
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wire when_SdramCtrl_l265_22;
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wire when_Utils_l1017_12;
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wire when_SdramCtrl_l265_23;
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wire when_Utils_l1017_13;
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wire when_SdramCtrl_l265_24;
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wire when_Utils_l1017_14;
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wire when_SdramCtrl_l265_25;
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wire when_Utils_l1017_15;
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wire when_SdramCtrl_l265_26;
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wire chip_cmd_valid;
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wire chip_cmd_ready;
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wire [2:0] chip_cmd_payload_task;
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wire [1:0] chip_cmd_payload_bank;
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wire [12:0] chip_cmd_payload_rowColumn;
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wire [15:0] chip_cmd_payload_data;
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wire [1:0] chip_cmd_payload_mask;
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wire chip_cmd_payload_context;
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reg [12:0] chip_sdram_ADDR;
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reg [1:0] chip_sdram_BA;
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reg [15:0] chip_sdram_DQ_read;
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reg [15:0] chip_sdram_DQ_write;
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reg [15:0] chip_sdram_DQ_writeEnable;
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reg [1:0] chip_sdram_DQM;
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reg chip_sdram_CASn;
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reg chip_sdram_CKE;
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reg chip_sdram_CSn;
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reg chip_sdram_RASn;
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reg chip_sdram_WEn;
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wire chip_remoteCke;
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wire chip_readHistory_0;
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wire chip_readHistory_1;
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wire chip_readHistory_2;
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wire chip_readHistory_3;
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wire chip_readHistory_4;
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wire chip_readHistory_5;
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wire _zz_chip_readHistory_0;
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reg _zz_chip_readHistory_1;
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reg _zz_chip_readHistory_2;
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reg _zz_chip_readHistory_3;
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reg _zz_chip_readHistory_4;
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reg _zz_chip_readHistory_5;
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reg chip_cmd_payload_context_delay_1;
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reg chip_cmd_payload_context_delay_2;
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reg chip_cmd_payload_context_delay_3;
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reg chip_cmd_payload_context_delay_4;
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reg chip_contextDelayed;
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wire chip_sdramCkeNext;
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reg chip_sdramCkeInternal;
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reg chip_sdramCkeInternal_regNext;
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wire _zz_chip_sdram_DQM;
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wire chip_backupIn_valid;
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wire chip_backupIn_ready;
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wire [15:0] chip_backupIn_payload_data;
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wire chip_backupIn_payload_context;
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`ifndef SYNTHESIS
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reg [127:0] frontend_rsp_payload_task_string;
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reg [111:0] frontend_state_string;
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reg [127:0] _zz_frontend_rsp_payload_task_string;
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reg [127:0] bubbleInserter_cmd_payload_task_string;
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reg [127:0] frontend_rsp_rData_task_string;
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reg [127:0] bubbleInserter_rsp_payload_task_string;
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reg [127:0] _zz_bubbleInserter_rsp_payload_task_string;
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reg [127:0] chip_cmd_payload_task_string;
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`endif
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assign _zz_refresh_counter_valueNext_1 = refresh_counter_willIncrement;
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assign _zz_refresh_counter_valueNext = {9'd0, _zz_refresh_counter_valueNext_1};
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assign _zz_frontend_bootRefreshCounter_valueNext_1 = frontend_bootRefreshCounter_willIncrement;
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assign _zz_frontend_bootRefreshCounter_valueNext = {2'd0, _zz_frontend_bootRefreshCounter_valueNext_1};
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StreamFifoLowLatency chip_backupIn_fifo (
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.io_push_valid (chip_backupIn_valid ), //i
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.io_push_ready (chip_backupIn_fifo_io_push_ready ), //o
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.io_push_payload_data (chip_backupIn_payload_data[15:0] ), //i
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.io_push_payload_context (chip_backupIn_payload_context ), //i
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.io_pop_valid (chip_backupIn_fifo_io_pop_valid ), //o
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.io_pop_ready (io_bus_rsp_ready ), //i
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.io_pop_payload_data (chip_backupIn_fifo_io_pop_payload_data[15:0]), //o
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.io_pop_payload_context (chip_backupIn_fifo_io_pop_payload_context ), //o
|
|
.io_flush (chip_backupIn_fifo_io_flush ), //i
|
|
.io_occupancy (chip_backupIn_fifo_io_occupancy[1:0] ), //o
|
|
.io_availability (chip_backupIn_fifo_io_availability[1:0] ), //o
|
|
.clk (clk ), //i
|
|
.reset (reset ) //i
|
|
);
|
|
always @(*) begin
|
|
case(frontend_address_bank)
|
|
2'b00 : begin
|
|
_zz__zz_when_SdramCtrl_l224 = frontend_banks_0_active;
|
|
_zz_when_SdramCtrl_l224_1 = frontend_banks_0_row;
|
|
end
|
|
2'b01 : begin
|
|
_zz__zz_when_SdramCtrl_l224 = frontend_banks_1_active;
|
|
_zz_when_SdramCtrl_l224_1 = frontend_banks_1_row;
|
|
end
|
|
2'b10 : begin
|
|
_zz__zz_when_SdramCtrl_l224 = frontend_banks_2_active;
|
|
_zz_when_SdramCtrl_l224_1 = frontend_banks_2_row;
|
|
end
|
|
default : begin
|
|
_zz__zz_when_SdramCtrl_l224 = frontend_banks_3_active;
|
|
_zz_when_SdramCtrl_l224_1 = frontend_banks_3_row;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @(*) begin
|
|
case(bubbleInserter_cmd_payload_bank)
|
|
2'b00 : begin
|
|
_zz_bubbleInserter_insertBubble = bubbleInserter_timings_banks_0_precharge_busy;
|
|
_zz_bubbleInserter_insertBubble_1 = bubbleInserter_timings_banks_0_active_busy;
|
|
end
|
|
2'b01 : begin
|
|
_zz_bubbleInserter_insertBubble = bubbleInserter_timings_banks_1_precharge_busy;
|
|
_zz_bubbleInserter_insertBubble_1 = bubbleInserter_timings_banks_1_active_busy;
|
|
end
|
|
2'b10 : begin
|
|
_zz_bubbleInserter_insertBubble = bubbleInserter_timings_banks_2_precharge_busy;
|
|
_zz_bubbleInserter_insertBubble_1 = bubbleInserter_timings_banks_2_active_busy;
|
|
end
|
|
default : begin
|
|
_zz_bubbleInserter_insertBubble = bubbleInserter_timings_banks_3_precharge_busy;
|
|
_zz_bubbleInserter_insertBubble_1 = bubbleInserter_timings_banks_3_active_busy;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
`ifndef SYNTHESIS
|
|
always @(*) begin
|
|
case(frontend_rsp_payload_task)
|
|
SdramCtrlBackendTask_MODE : frontend_rsp_payload_task_string = "MODE ";
|
|
SdramCtrlBackendTask_PRECHARGE_ALL : frontend_rsp_payload_task_string = "PRECHARGE_ALL ";
|
|
SdramCtrlBackendTask_PRECHARGE_SINGLE : frontend_rsp_payload_task_string = "PRECHARGE_SINGLE";
|
|
SdramCtrlBackendTask_REFRESH : frontend_rsp_payload_task_string = "REFRESH ";
|
|
SdramCtrlBackendTask_ACTIVE : frontend_rsp_payload_task_string = "ACTIVE ";
|
|
SdramCtrlBackendTask_READ : frontend_rsp_payload_task_string = "READ ";
|
|
SdramCtrlBackendTask_WRITE : frontend_rsp_payload_task_string = "WRITE ";
|
|
default : frontend_rsp_payload_task_string = "????????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(frontend_state)
|
|
SdramCtrlFrontendState_BOOT_PRECHARGE : frontend_state_string = "BOOT_PRECHARGE";
|
|
SdramCtrlFrontendState_BOOT_REFRESH : frontend_state_string = "BOOT_REFRESH ";
|
|
SdramCtrlFrontendState_BOOT_MODE : frontend_state_string = "BOOT_MODE ";
|
|
SdramCtrlFrontendState_RUN : frontend_state_string = "RUN ";
|
|
default : frontend_state_string = "??????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_frontend_rsp_payload_task)
|
|
SdramCtrlBackendTask_MODE : _zz_frontend_rsp_payload_task_string = "MODE ";
|
|
SdramCtrlBackendTask_PRECHARGE_ALL : _zz_frontend_rsp_payload_task_string = "PRECHARGE_ALL ";
|
|
SdramCtrlBackendTask_PRECHARGE_SINGLE : _zz_frontend_rsp_payload_task_string = "PRECHARGE_SINGLE";
|
|
SdramCtrlBackendTask_REFRESH : _zz_frontend_rsp_payload_task_string = "REFRESH ";
|
|
SdramCtrlBackendTask_ACTIVE : _zz_frontend_rsp_payload_task_string = "ACTIVE ";
|
|
SdramCtrlBackendTask_READ : _zz_frontend_rsp_payload_task_string = "READ ";
|
|
SdramCtrlBackendTask_WRITE : _zz_frontend_rsp_payload_task_string = "WRITE ";
|
|
default : _zz_frontend_rsp_payload_task_string = "????????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(bubbleInserter_cmd_payload_task)
|
|
SdramCtrlBackendTask_MODE : bubbleInserter_cmd_payload_task_string = "MODE ";
|
|
SdramCtrlBackendTask_PRECHARGE_ALL : bubbleInserter_cmd_payload_task_string = "PRECHARGE_ALL ";
|
|
SdramCtrlBackendTask_PRECHARGE_SINGLE : bubbleInserter_cmd_payload_task_string = "PRECHARGE_SINGLE";
|
|
SdramCtrlBackendTask_REFRESH : bubbleInserter_cmd_payload_task_string = "REFRESH ";
|
|
SdramCtrlBackendTask_ACTIVE : bubbleInserter_cmd_payload_task_string = "ACTIVE ";
|
|
SdramCtrlBackendTask_READ : bubbleInserter_cmd_payload_task_string = "READ ";
|
|
SdramCtrlBackendTask_WRITE : bubbleInserter_cmd_payload_task_string = "WRITE ";
|
|
default : bubbleInserter_cmd_payload_task_string = "????????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(frontend_rsp_rData_task)
|
|
SdramCtrlBackendTask_MODE : frontend_rsp_rData_task_string = "MODE ";
|
|
SdramCtrlBackendTask_PRECHARGE_ALL : frontend_rsp_rData_task_string = "PRECHARGE_ALL ";
|
|
SdramCtrlBackendTask_PRECHARGE_SINGLE : frontend_rsp_rData_task_string = "PRECHARGE_SINGLE";
|
|
SdramCtrlBackendTask_REFRESH : frontend_rsp_rData_task_string = "REFRESH ";
|
|
SdramCtrlBackendTask_ACTIVE : frontend_rsp_rData_task_string = "ACTIVE ";
|
|
SdramCtrlBackendTask_READ : frontend_rsp_rData_task_string = "READ ";
|
|
SdramCtrlBackendTask_WRITE : frontend_rsp_rData_task_string = "WRITE ";
|
|
default : frontend_rsp_rData_task_string = "????????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(bubbleInserter_rsp_payload_task)
|
|
SdramCtrlBackendTask_MODE : bubbleInserter_rsp_payload_task_string = "MODE ";
|
|
SdramCtrlBackendTask_PRECHARGE_ALL : bubbleInserter_rsp_payload_task_string = "PRECHARGE_ALL ";
|
|
SdramCtrlBackendTask_PRECHARGE_SINGLE : bubbleInserter_rsp_payload_task_string = "PRECHARGE_SINGLE";
|
|
SdramCtrlBackendTask_REFRESH : bubbleInserter_rsp_payload_task_string = "REFRESH ";
|
|
SdramCtrlBackendTask_ACTIVE : bubbleInserter_rsp_payload_task_string = "ACTIVE ";
|
|
SdramCtrlBackendTask_READ : bubbleInserter_rsp_payload_task_string = "READ ";
|
|
SdramCtrlBackendTask_WRITE : bubbleInserter_rsp_payload_task_string = "WRITE ";
|
|
default : bubbleInserter_rsp_payload_task_string = "????????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_bubbleInserter_rsp_payload_task)
|
|
SdramCtrlBackendTask_MODE : _zz_bubbleInserter_rsp_payload_task_string = "MODE ";
|
|
SdramCtrlBackendTask_PRECHARGE_ALL : _zz_bubbleInserter_rsp_payload_task_string = "PRECHARGE_ALL ";
|
|
SdramCtrlBackendTask_PRECHARGE_SINGLE : _zz_bubbleInserter_rsp_payload_task_string = "PRECHARGE_SINGLE";
|
|
SdramCtrlBackendTask_REFRESH : _zz_bubbleInserter_rsp_payload_task_string = "REFRESH ";
|
|
SdramCtrlBackendTask_ACTIVE : _zz_bubbleInserter_rsp_payload_task_string = "ACTIVE ";
|
|
SdramCtrlBackendTask_READ : _zz_bubbleInserter_rsp_payload_task_string = "READ ";
|
|
SdramCtrlBackendTask_WRITE : _zz_bubbleInserter_rsp_payload_task_string = "WRITE ";
|
|
default : _zz_bubbleInserter_rsp_payload_task_string = "????????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(chip_cmd_payload_task)
|
|
SdramCtrlBackendTask_MODE : chip_cmd_payload_task_string = "MODE ";
|
|
SdramCtrlBackendTask_PRECHARGE_ALL : chip_cmd_payload_task_string = "PRECHARGE_ALL ";
|
|
SdramCtrlBackendTask_PRECHARGE_SINGLE : chip_cmd_payload_task_string = "PRECHARGE_SINGLE";
|
|
SdramCtrlBackendTask_REFRESH : chip_cmd_payload_task_string = "REFRESH ";
|
|
SdramCtrlBackendTask_ACTIVE : chip_cmd_payload_task_string = "ACTIVE ";
|
|
SdramCtrlBackendTask_READ : chip_cmd_payload_task_string = "READ ";
|
|
SdramCtrlBackendTask_WRITE : chip_cmd_payload_task_string = "WRITE ";
|
|
default : chip_cmd_payload_task_string = "????????????????";
|
|
endcase
|
|
end
|
|
`endif
|
|
|
|
assign refresh_counter_willClear = 1'b0;
|
|
assign refresh_counter_willOverflowIfInc = (refresh_counter_value == 10'h30d);
|
|
assign refresh_counter_willOverflow = (refresh_counter_willOverflowIfInc && refresh_counter_willIncrement);
|
|
always @(*) begin
|
|
if(refresh_counter_willOverflow) begin
|
|
refresh_counter_valueNext = 10'h000;
|
|
end else begin
|
|
refresh_counter_valueNext = (refresh_counter_value + _zz_refresh_counter_valueNext);
|
|
end
|
|
if(refresh_counter_willClear) begin
|
|
refresh_counter_valueNext = 10'h000;
|
|
end
|
|
end
|
|
|
|
assign refresh_counter_willIncrement = 1'b1;
|
|
assign when_SdramCtrl_l146 = (! powerup_done);
|
|
assign _zz_when_SdramCtrl_l148[14 : 0] = 15'h7fff;
|
|
assign when_SdramCtrl_l148 = (powerup_counter == _zz_when_SdramCtrl_l148);
|
|
assign _zz_frontend_address_column = io_bus_cmd_payload_address;
|
|
assign frontend_address_column = _zz_frontend_address_column[8 : 0];
|
|
assign frontend_address_bank = _zz_frontend_address_column[10 : 9];
|
|
assign frontend_address_row = _zz_frontend_address_column[23 : 11];
|
|
always @(*) begin
|
|
frontend_rsp_valid = 1'b0;
|
|
case(frontend_state)
|
|
SdramCtrlFrontendState_BOOT_PRECHARGE : begin
|
|
if(powerup_done) begin
|
|
frontend_rsp_valid = 1'b1;
|
|
end
|
|
end
|
|
SdramCtrlFrontendState_BOOT_REFRESH : begin
|
|
frontend_rsp_valid = 1'b1;
|
|
end
|
|
SdramCtrlFrontendState_BOOT_MODE : begin
|
|
frontend_rsp_valid = 1'b1;
|
|
end
|
|
default : begin
|
|
if(refresh_pending) begin
|
|
frontend_rsp_valid = 1'b1;
|
|
end else begin
|
|
if(io_bus_cmd_valid) begin
|
|
frontend_rsp_valid = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @(*) begin
|
|
frontend_rsp_payload_task = SdramCtrlBackendTask_REFRESH;
|
|
case(frontend_state)
|
|
SdramCtrlFrontendState_BOOT_PRECHARGE : begin
|
|
frontend_rsp_payload_task = SdramCtrlBackendTask_PRECHARGE_ALL;
|
|
end
|
|
SdramCtrlFrontendState_BOOT_REFRESH : begin
|
|
frontend_rsp_payload_task = SdramCtrlBackendTask_REFRESH;
|
|
end
|
|
SdramCtrlFrontendState_BOOT_MODE : begin
|
|
frontend_rsp_payload_task = SdramCtrlBackendTask_MODE;
|
|
end
|
|
default : begin
|
|
if(refresh_pending) begin
|
|
if(when_SdramCtrl_l210) begin
|
|
frontend_rsp_payload_task = SdramCtrlBackendTask_PRECHARGE_ALL;
|
|
end else begin
|
|
frontend_rsp_payload_task = SdramCtrlBackendTask_REFRESH;
|
|
end
|
|
end else begin
|
|
if(io_bus_cmd_valid) begin
|
|
if(when_SdramCtrl_l224) begin
|
|
frontend_rsp_payload_task = SdramCtrlBackendTask_PRECHARGE_SINGLE;
|
|
end else begin
|
|
if(when_SdramCtrl_l229) begin
|
|
frontend_rsp_payload_task = SdramCtrlBackendTask_ACTIVE;
|
|
end else begin
|
|
frontend_rsp_payload_task = _zz_frontend_rsp_payload_task;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign frontend_rsp_payload_bank = frontend_address_bank;
|
|
always @(*) begin
|
|
frontend_rsp_payload_rowColumn = frontend_address_row;
|
|
case(frontend_state)
|
|
SdramCtrlFrontendState_BOOT_PRECHARGE : begin
|
|
end
|
|
SdramCtrlFrontendState_BOOT_REFRESH : begin
|
|
end
|
|
SdramCtrlFrontendState_BOOT_MODE : begin
|
|
end
|
|
default : begin
|
|
if(!refresh_pending) begin
|
|
if(io_bus_cmd_valid) begin
|
|
if(!when_SdramCtrl_l224) begin
|
|
if(!when_SdramCtrl_l229) begin
|
|
frontend_rsp_payload_rowColumn = {4'd0, frontend_address_column};
|
|
end
|
|
end
|
|
end
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign frontend_rsp_payload_data = io_bus_cmd_payload_data;
|
|
assign frontend_rsp_payload_mask = io_bus_cmd_payload_mask;
|
|
assign frontend_rsp_payload_context = io_bus_cmd_payload_context;
|
|
always @(*) begin
|
|
io_bus_cmd_ready = 1'b0;
|
|
case(frontend_state)
|
|
SdramCtrlFrontendState_BOOT_PRECHARGE : begin
|
|
end
|
|
SdramCtrlFrontendState_BOOT_REFRESH : begin
|
|
end
|
|
SdramCtrlFrontendState_BOOT_MODE : begin
|
|
end
|
|
default : begin
|
|
if(!refresh_pending) begin
|
|
if(io_bus_cmd_valid) begin
|
|
if(!when_SdramCtrl_l224) begin
|
|
if(!when_SdramCtrl_l229) begin
|
|
io_bus_cmd_ready = frontend_rsp_ready;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @(*) begin
|
|
frontend_bootRefreshCounter_willIncrement = 1'b0;
|
|
case(frontend_state)
|
|
SdramCtrlFrontendState_BOOT_PRECHARGE : begin
|
|
end
|
|
SdramCtrlFrontendState_BOOT_REFRESH : begin
|
|
if(frontend_rsp_ready) begin
|
|
frontend_bootRefreshCounter_willIncrement = 1'b1;
|
|
end
|
|
end
|
|
SdramCtrlFrontendState_BOOT_MODE : begin
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign frontend_bootRefreshCounter_willClear = 1'b0;
|
|
assign frontend_bootRefreshCounter_willOverflowIfInc = (frontend_bootRefreshCounter_value == 3'b111);
|
|
assign frontend_bootRefreshCounter_willOverflow = (frontend_bootRefreshCounter_willOverflowIfInc && frontend_bootRefreshCounter_willIncrement);
|
|
always @(*) begin
|
|
frontend_bootRefreshCounter_valueNext = (frontend_bootRefreshCounter_value + _zz_frontend_bootRefreshCounter_valueNext);
|
|
if(frontend_bootRefreshCounter_willClear) begin
|
|
frontend_bootRefreshCounter_valueNext = 3'b000;
|
|
end
|
|
end
|
|
|
|
assign when_SdramCtrl_l210 = (((frontend_banks_0_active || frontend_banks_1_active) || frontend_banks_2_active) || frontend_banks_3_active);
|
|
assign _zz_when_SdramCtrl_l224 = _zz__zz_when_SdramCtrl_l224;
|
|
assign _zz_1 = ({3'd0,1'b1} <<< frontend_address_bank);
|
|
assign _zz_2 = _zz_1[0];
|
|
assign _zz_3 = _zz_1[1];
|
|
assign _zz_4 = _zz_1[2];
|
|
assign _zz_5 = _zz_1[3];
|
|
assign when_SdramCtrl_l224 = (_zz_when_SdramCtrl_l224 && (_zz_when_SdramCtrl_l224_1 != frontend_address_row));
|
|
assign _zz_frontend_rsp_payload_task = (io_bus_cmd_payload_write ? SdramCtrlBackendTask_WRITE : SdramCtrlBackendTask_READ);
|
|
assign when_SdramCtrl_l229 = (! _zz_when_SdramCtrl_l224);
|
|
always @(*) begin
|
|
frontend_rsp_ready = bubbleInserter_cmd_ready;
|
|
if(when_Stream_l369) begin
|
|
frontend_rsp_ready = 1'b1;
|
|
end
|
|
end
|
|
|
|
assign when_Stream_l369 = (! bubbleInserter_cmd_valid);
|
|
assign bubbleInserter_cmd_valid = frontend_rsp_rValid;
|
|
assign bubbleInserter_cmd_payload_task = frontend_rsp_rData_task;
|
|
assign bubbleInserter_cmd_payload_bank = frontend_rsp_rData_bank;
|
|
assign bubbleInserter_cmd_payload_rowColumn = frontend_rsp_rData_rowColumn;
|
|
assign bubbleInserter_cmd_payload_data = frontend_rsp_rData_data;
|
|
assign bubbleInserter_cmd_payload_mask = frontend_rsp_rData_mask;
|
|
assign bubbleInserter_cmd_payload_context = frontend_rsp_rData_context;
|
|
always @(*) begin
|
|
bubbleInserter_insertBubble = 1'b0;
|
|
if(bubbleInserter_cmd_valid) begin
|
|
case(bubbleInserter_cmd_payload_task)
|
|
SdramCtrlBackendTask_MODE : begin
|
|
bubbleInserter_insertBubble = bubbleInserter_timings_banks_0_active_busy;
|
|
end
|
|
SdramCtrlBackendTask_PRECHARGE_ALL : begin
|
|
bubbleInserter_insertBubble = (|{bubbleInserter_timings_banks_3_precharge_busy,{bubbleInserter_timings_banks_2_precharge_busy,{bubbleInserter_timings_banks_1_precharge_busy,bubbleInserter_timings_banks_0_precharge_busy}}});
|
|
end
|
|
SdramCtrlBackendTask_PRECHARGE_SINGLE : begin
|
|
bubbleInserter_insertBubble = _zz_bubbleInserter_insertBubble;
|
|
end
|
|
SdramCtrlBackendTask_REFRESH : begin
|
|
bubbleInserter_insertBubble = (|{bubbleInserter_timings_banks_3_active_busy,{bubbleInserter_timings_banks_2_active_busy,{bubbleInserter_timings_banks_1_active_busy,bubbleInserter_timings_banks_0_active_busy}}});
|
|
end
|
|
SdramCtrlBackendTask_ACTIVE : begin
|
|
bubbleInserter_insertBubble = _zz_bubbleInserter_insertBubble_1;
|
|
end
|
|
SdramCtrlBackendTask_READ : begin
|
|
bubbleInserter_insertBubble = bubbleInserter_timings_read_busy;
|
|
end
|
|
default : begin
|
|
bubbleInserter_insertBubble = bubbleInserter_timings_write_busy;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
assign _zz_bubbleInserter_cmd_ready = (! bubbleInserter_insertBubble);
|
|
assign bubbleInserter_cmd_ready = (bubbleInserter_rsp_ready && _zz_bubbleInserter_cmd_ready);
|
|
assign _zz_bubbleInserter_rsp_payload_task = bubbleInserter_cmd_payload_task;
|
|
assign bubbleInserter_rsp_valid = (bubbleInserter_cmd_valid && _zz_bubbleInserter_cmd_ready);
|
|
assign bubbleInserter_rsp_payload_task = _zz_bubbleInserter_rsp_payload_task;
|
|
assign bubbleInserter_rsp_payload_bank = bubbleInserter_cmd_payload_bank;
|
|
assign bubbleInserter_rsp_payload_rowColumn = bubbleInserter_cmd_payload_rowColumn;
|
|
assign bubbleInserter_rsp_payload_data = bubbleInserter_cmd_payload_data;
|
|
assign bubbleInserter_rsp_payload_mask = bubbleInserter_cmd_payload_mask;
|
|
assign bubbleInserter_rsp_payload_context = bubbleInserter_cmd_payload_context;
|
|
assign bubbleInserter_timings_read_busy = (bubbleInserter_timings_read_counter != 1'b0);
|
|
assign when_SdramCtrl_l256 = (bubbleInserter_timings_read_busy && bubbleInserter_rsp_ready);
|
|
assign bubbleInserter_timings_write_busy = (bubbleInserter_timings_write_counter != 3'b000);
|
|
assign when_SdramCtrl_l256_1 = (bubbleInserter_timings_write_busy && bubbleInserter_rsp_ready);
|
|
assign bubbleInserter_timings_banks_0_precharge_busy = (bubbleInserter_timings_banks_0_precharge_counter != 3'b000);
|
|
assign when_SdramCtrl_l256_2 = (bubbleInserter_timings_banks_0_precharge_busy && bubbleInserter_rsp_ready);
|
|
assign bubbleInserter_timings_banks_0_active_busy = (bubbleInserter_timings_banks_0_active_counter != 3'b000);
|
|
assign when_SdramCtrl_l256_3 = (bubbleInserter_timings_banks_0_active_busy && bubbleInserter_rsp_ready);
|
|
assign bubbleInserter_timings_banks_1_precharge_busy = (bubbleInserter_timings_banks_1_precharge_counter != 3'b000);
|
|
assign when_SdramCtrl_l256_4 = (bubbleInserter_timings_banks_1_precharge_busy && bubbleInserter_rsp_ready);
|
|
assign bubbleInserter_timings_banks_1_active_busy = (bubbleInserter_timings_banks_1_active_counter != 3'b000);
|
|
assign when_SdramCtrl_l256_5 = (bubbleInserter_timings_banks_1_active_busy && bubbleInserter_rsp_ready);
|
|
assign bubbleInserter_timings_banks_2_precharge_busy = (bubbleInserter_timings_banks_2_precharge_counter != 3'b000);
|
|
assign when_SdramCtrl_l256_6 = (bubbleInserter_timings_banks_2_precharge_busy && bubbleInserter_rsp_ready);
|
|
assign bubbleInserter_timings_banks_2_active_busy = (bubbleInserter_timings_banks_2_active_counter != 3'b000);
|
|
assign when_SdramCtrl_l256_7 = (bubbleInserter_timings_banks_2_active_busy && bubbleInserter_rsp_ready);
|
|
assign bubbleInserter_timings_banks_3_precharge_busy = (bubbleInserter_timings_banks_3_precharge_counter != 3'b000);
|
|
assign when_SdramCtrl_l256_8 = (bubbleInserter_timings_banks_3_precharge_busy && bubbleInserter_rsp_ready);
|
|
assign bubbleInserter_timings_banks_3_active_busy = (bubbleInserter_timings_banks_3_active_counter != 3'b000);
|
|
assign when_SdramCtrl_l256_9 = (bubbleInserter_timings_banks_3_active_busy && bubbleInserter_rsp_ready);
|
|
assign when_SdramCtrl_l265 = (bubbleInserter_timings_banks_0_active_counter <= 3'b001);
|
|
assign when_SdramCtrl_l265_1 = (bubbleInserter_timings_banks_1_active_counter <= 3'b001);
|
|
assign when_SdramCtrl_l265_2 = (bubbleInserter_timings_banks_2_active_counter <= 3'b001);
|
|
assign when_SdramCtrl_l265_3 = (bubbleInserter_timings_banks_3_active_counter <= 3'b001);
|
|
assign when_SdramCtrl_l265_4 = (bubbleInserter_timings_banks_0_active_counter <= 3'b001);
|
|
assign when_Utils_l1017 = (bubbleInserter_cmd_payload_bank == 2'b00);
|
|
assign when_SdramCtrl_l265_5 = (bubbleInserter_timings_banks_0_active_counter <= 3'b001);
|
|
assign when_Utils_l1017_1 = (bubbleInserter_cmd_payload_bank == 2'b01);
|
|
assign when_SdramCtrl_l265_6 = (bubbleInserter_timings_banks_1_active_counter <= 3'b001);
|
|
assign when_Utils_l1017_2 = (bubbleInserter_cmd_payload_bank == 2'b10);
|
|
assign when_SdramCtrl_l265_7 = (bubbleInserter_timings_banks_2_active_counter <= 3'b001);
|
|
assign when_Utils_l1017_3 = (bubbleInserter_cmd_payload_bank == 2'b11);
|
|
assign when_SdramCtrl_l265_8 = (bubbleInserter_timings_banks_3_active_counter <= 3'b001);
|
|
assign when_SdramCtrl_l265_9 = (bubbleInserter_timings_banks_0_active_counter <= 3'b101);
|
|
assign when_SdramCtrl_l265_10 = (bubbleInserter_timings_banks_1_active_counter <= 3'b101);
|
|
assign when_SdramCtrl_l265_11 = (bubbleInserter_timings_banks_2_active_counter <= 3'b101);
|
|
assign when_SdramCtrl_l265_12 = (bubbleInserter_timings_banks_3_active_counter <= 3'b101);
|
|
assign when_SdramCtrl_l265_13 = (bubbleInserter_timings_write_counter <= 3'b001);
|
|
assign when_Utils_l1017_4 = (bubbleInserter_cmd_payload_bank == 2'b00);
|
|
assign when_SdramCtrl_l265_14 = (bubbleInserter_timings_banks_0_precharge_counter <= 3'b100);
|
|
assign when_Utils_l1017_5 = (bubbleInserter_cmd_payload_bank == 2'b01);
|
|
assign when_SdramCtrl_l265_15 = (bubbleInserter_timings_banks_1_precharge_counter <= 3'b100);
|
|
assign when_Utils_l1017_6 = (bubbleInserter_cmd_payload_bank == 2'b10);
|
|
assign when_SdramCtrl_l265_16 = (bubbleInserter_timings_banks_2_precharge_counter <= 3'b100);
|
|
assign when_Utils_l1017_7 = (bubbleInserter_cmd_payload_bank == 2'b11);
|
|
assign when_SdramCtrl_l265_17 = (bubbleInserter_timings_banks_3_precharge_counter <= 3'b100);
|
|
assign when_Utils_l1017_8 = (bubbleInserter_cmd_payload_bank == 2'b00);
|
|
assign when_SdramCtrl_l265_18 = (bubbleInserter_timings_banks_0_active_counter <= 3'b101);
|
|
assign when_Utils_l1017_9 = (bubbleInserter_cmd_payload_bank == 2'b01);
|
|
assign when_SdramCtrl_l265_19 = (bubbleInserter_timings_banks_1_active_counter <= 3'b101);
|
|
assign when_Utils_l1017_10 = (bubbleInserter_cmd_payload_bank == 2'b10);
|
|
assign when_SdramCtrl_l265_20 = (bubbleInserter_timings_banks_2_active_counter <= 3'b101);
|
|
assign when_Utils_l1017_11 = (bubbleInserter_cmd_payload_bank == 2'b11);
|
|
assign when_SdramCtrl_l265_21 = (bubbleInserter_timings_banks_3_active_counter <= 3'b101);
|
|
assign when_SdramCtrl_l265_22 = (bubbleInserter_timings_write_counter <= 3'b100);
|
|
assign when_Utils_l1017_12 = (bubbleInserter_cmd_payload_bank == 2'b00);
|
|
assign when_SdramCtrl_l265_23 = (bubbleInserter_timings_banks_0_precharge_counter <= 3'b001);
|
|
assign when_Utils_l1017_13 = (bubbleInserter_cmd_payload_bank == 2'b01);
|
|
assign when_SdramCtrl_l265_24 = (bubbleInserter_timings_banks_1_precharge_counter <= 3'b001);
|
|
assign when_Utils_l1017_14 = (bubbleInserter_cmd_payload_bank == 2'b10);
|
|
assign when_SdramCtrl_l265_25 = (bubbleInserter_timings_banks_2_precharge_counter <= 3'b001);
|
|
assign when_Utils_l1017_15 = (bubbleInserter_cmd_payload_bank == 2'b11);
|
|
assign when_SdramCtrl_l265_26 = (bubbleInserter_timings_banks_3_precharge_counter <= 3'b001);
|
|
assign chip_cmd_valid = bubbleInserter_rsp_valid;
|
|
assign bubbleInserter_rsp_ready = chip_cmd_ready;
|
|
assign chip_cmd_payload_task = bubbleInserter_rsp_payload_task;
|
|
assign chip_cmd_payload_bank = bubbleInserter_rsp_payload_bank;
|
|
assign chip_cmd_payload_rowColumn = bubbleInserter_rsp_payload_rowColumn;
|
|
assign chip_cmd_payload_data = bubbleInserter_rsp_payload_data;
|
|
assign chip_cmd_payload_mask = bubbleInserter_rsp_payload_mask;
|
|
assign chip_cmd_payload_context = bubbleInserter_rsp_payload_context;
|
|
assign io_sdram_ADDR = chip_sdram_ADDR;
|
|
assign io_sdram_BA = chip_sdram_BA;
|
|
assign io_sdram_DQ_write = chip_sdram_DQ_write;
|
|
assign io_sdram_DQ_writeEnable = chip_sdram_DQ_writeEnable;
|
|
assign io_sdram_DQM = chip_sdram_DQM;
|
|
assign io_sdram_CASn = chip_sdram_CASn;
|
|
assign io_sdram_CKE = chip_sdram_CKE;
|
|
assign io_sdram_CSn = chip_sdram_CSn;
|
|
assign io_sdram_RASn = chip_sdram_RASn;
|
|
assign io_sdram_WEn = chip_sdram_WEn;
|
|
assign _zz_chip_readHistory_0 = (chip_cmd_valid && ((chip_cmd_payload_task == SdramCtrlBackendTask_READ) || 1'b0));
|
|
assign chip_readHistory_0 = _zz_chip_readHistory_0;
|
|
assign chip_readHistory_1 = _zz_chip_readHistory_1;
|
|
assign chip_readHistory_2 = _zz_chip_readHistory_2;
|
|
assign chip_readHistory_3 = _zz_chip_readHistory_3;
|
|
assign chip_readHistory_4 = _zz_chip_readHistory_4;
|
|
assign chip_readHistory_5 = _zz_chip_readHistory_5;
|
|
assign chip_sdramCkeNext = (! ((|{chip_readHistory_5,{chip_readHistory_4,{chip_readHistory_3,{chip_readHistory_2,{chip_readHistory_1,chip_readHistory_0}}}}}) && (! io_bus_rsp_ready)));
|
|
assign chip_remoteCke = chip_sdramCkeInternal_regNext;
|
|
assign _zz_chip_sdram_DQM = (! chip_readHistory_1);
|
|
assign chip_backupIn_valid = (chip_readHistory_5 && chip_remoteCke);
|
|
assign chip_backupIn_payload_data = chip_sdram_DQ_read;
|
|
assign chip_backupIn_payload_context = chip_contextDelayed;
|
|
assign chip_backupIn_ready = chip_backupIn_fifo_io_push_ready;
|
|
assign io_bus_rsp_valid = chip_backupIn_fifo_io_pop_valid;
|
|
assign io_bus_rsp_payload_data = chip_backupIn_fifo_io_pop_payload_data;
|
|
assign io_bus_rsp_payload_context = chip_backupIn_fifo_io_pop_payload_context;
|
|
assign chip_cmd_ready = chip_remoteCke;
|
|
assign chip_backupIn_fifo_io_flush = 1'b0;
|
|
always @(posedge clk or posedge reset) begin
|
|
if(reset) begin
|
|
refresh_counter_value <= 10'h000;
|
|
refresh_pending <= 1'b0;
|
|
powerup_counter <= 15'h0000;
|
|
powerup_done <= 1'b0;
|
|
frontend_banks_0_active <= 1'b0;
|
|
frontend_banks_1_active <= 1'b0;
|
|
frontend_banks_2_active <= 1'b0;
|
|
frontend_banks_3_active <= 1'b0;
|
|
frontend_state <= SdramCtrlFrontendState_BOOT_PRECHARGE;
|
|
frontend_bootRefreshCounter_value <= 3'b000;
|
|
frontend_rsp_rValid <= 1'b0;
|
|
bubbleInserter_timings_read_counter <= 1'b0;
|
|
bubbleInserter_timings_write_counter <= 3'b000;
|
|
bubbleInserter_timings_banks_0_precharge_counter <= 3'b000;
|
|
bubbleInserter_timings_banks_0_active_counter <= 3'b000;
|
|
bubbleInserter_timings_banks_1_precharge_counter <= 3'b000;
|
|
bubbleInserter_timings_banks_1_active_counter <= 3'b000;
|
|
bubbleInserter_timings_banks_2_precharge_counter <= 3'b000;
|
|
bubbleInserter_timings_banks_2_active_counter <= 3'b000;
|
|
bubbleInserter_timings_banks_3_precharge_counter <= 3'b000;
|
|
bubbleInserter_timings_banks_3_active_counter <= 3'b000;
|
|
_zz_chip_readHistory_1 <= 1'b0;
|
|
_zz_chip_readHistory_2 <= 1'b0;
|
|
_zz_chip_readHistory_3 <= 1'b0;
|
|
_zz_chip_readHistory_4 <= 1'b0;
|
|
_zz_chip_readHistory_5 <= 1'b0;
|
|
chip_sdramCkeInternal <= 1'b1;
|
|
chip_sdramCkeInternal_regNext <= 1'b1;
|
|
end else begin
|
|
refresh_counter_value <= refresh_counter_valueNext;
|
|
if(refresh_counter_willOverflow) begin
|
|
refresh_pending <= 1'b1;
|
|
end
|
|
if(when_SdramCtrl_l146) begin
|
|
powerup_counter <= (powerup_counter + 15'h0001);
|
|
if(when_SdramCtrl_l148) begin
|
|
powerup_done <= 1'b1;
|
|
end
|
|
end
|
|
frontend_bootRefreshCounter_value <= frontend_bootRefreshCounter_valueNext;
|
|
case(frontend_state)
|
|
SdramCtrlFrontendState_BOOT_PRECHARGE : begin
|
|
if(powerup_done) begin
|
|
if(frontend_rsp_ready) begin
|
|
frontend_state <= SdramCtrlFrontendState_BOOT_REFRESH;
|
|
end
|
|
end
|
|
end
|
|
SdramCtrlFrontendState_BOOT_REFRESH : begin
|
|
if(frontend_rsp_ready) begin
|
|
if(frontend_bootRefreshCounter_willOverflowIfInc) begin
|
|
frontend_state <= SdramCtrlFrontendState_BOOT_MODE;
|
|
end
|
|
end
|
|
end
|
|
SdramCtrlFrontendState_BOOT_MODE : begin
|
|
if(frontend_rsp_ready) begin
|
|
frontend_state <= SdramCtrlFrontendState_RUN;
|
|
end
|
|
end
|
|
default : begin
|
|
if(refresh_pending) begin
|
|
if(when_SdramCtrl_l210) begin
|
|
if(frontend_rsp_ready) begin
|
|
frontend_banks_0_active <= 1'b0;
|
|
frontend_banks_1_active <= 1'b0;
|
|
frontend_banks_2_active <= 1'b0;
|
|
frontend_banks_3_active <= 1'b0;
|
|
end
|
|
end else begin
|
|
if(frontend_rsp_ready) begin
|
|
refresh_pending <= 1'b0;
|
|
end
|
|
end
|
|
end else begin
|
|
if(io_bus_cmd_valid) begin
|
|
if(when_SdramCtrl_l224) begin
|
|
if(frontend_rsp_ready) begin
|
|
if(_zz_2) begin
|
|
frontend_banks_0_active <= 1'b0;
|
|
end
|
|
if(_zz_3) begin
|
|
frontend_banks_1_active <= 1'b0;
|
|
end
|
|
if(_zz_4) begin
|
|
frontend_banks_2_active <= 1'b0;
|
|
end
|
|
if(_zz_5) begin
|
|
frontend_banks_3_active <= 1'b0;
|
|
end
|
|
end
|
|
end else begin
|
|
if(when_SdramCtrl_l229) begin
|
|
if(frontend_rsp_ready) begin
|
|
if(_zz_2) begin
|
|
frontend_banks_0_active <= 1'b1;
|
|
end
|
|
if(_zz_3) begin
|
|
frontend_banks_1_active <= 1'b1;
|
|
end
|
|
if(_zz_4) begin
|
|
frontend_banks_2_active <= 1'b1;
|
|
end
|
|
if(_zz_5) begin
|
|
frontend_banks_3_active <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
end
|
|
end
|
|
end
|
|
endcase
|
|
if(frontend_rsp_ready) begin
|
|
frontend_rsp_rValid <= frontend_rsp_valid;
|
|
end
|
|
if(when_SdramCtrl_l256) begin
|
|
bubbleInserter_timings_read_counter <= (bubbleInserter_timings_read_counter - 1'b1);
|
|
end
|
|
if(when_SdramCtrl_l256_1) begin
|
|
bubbleInserter_timings_write_counter <= (bubbleInserter_timings_write_counter - 3'b001);
|
|
end
|
|
if(when_SdramCtrl_l256_2) begin
|
|
bubbleInserter_timings_banks_0_precharge_counter <= (bubbleInserter_timings_banks_0_precharge_counter - 3'b001);
|
|
end
|
|
if(when_SdramCtrl_l256_3) begin
|
|
bubbleInserter_timings_banks_0_active_counter <= (bubbleInserter_timings_banks_0_active_counter - 3'b001);
|
|
end
|
|
if(when_SdramCtrl_l256_4) begin
|
|
bubbleInserter_timings_banks_1_precharge_counter <= (bubbleInserter_timings_banks_1_precharge_counter - 3'b001);
|
|
end
|
|
if(when_SdramCtrl_l256_5) begin
|
|
bubbleInserter_timings_banks_1_active_counter <= (bubbleInserter_timings_banks_1_active_counter - 3'b001);
|
|
end
|
|
if(when_SdramCtrl_l256_6) begin
|
|
bubbleInserter_timings_banks_2_precharge_counter <= (bubbleInserter_timings_banks_2_precharge_counter - 3'b001);
|
|
end
|
|
if(when_SdramCtrl_l256_7) begin
|
|
bubbleInserter_timings_banks_2_active_counter <= (bubbleInserter_timings_banks_2_active_counter - 3'b001);
|
|
end
|
|
if(when_SdramCtrl_l256_8) begin
|
|
bubbleInserter_timings_banks_3_precharge_counter <= (bubbleInserter_timings_banks_3_precharge_counter - 3'b001);
|
|
end
|
|
if(when_SdramCtrl_l256_9) begin
|
|
bubbleInserter_timings_banks_3_active_counter <= (bubbleInserter_timings_banks_3_active_counter - 3'b001);
|
|
end
|
|
if(bubbleInserter_cmd_valid) begin
|
|
case(bubbleInserter_cmd_payload_task)
|
|
SdramCtrlBackendTask_MODE : begin
|
|
if(bubbleInserter_cmd_ready) begin
|
|
if(when_SdramCtrl_l265) begin
|
|
bubbleInserter_timings_banks_0_active_counter <= 3'b001;
|
|
end
|
|
if(when_SdramCtrl_l265_1) begin
|
|
bubbleInserter_timings_banks_1_active_counter <= 3'b001;
|
|
end
|
|
if(when_SdramCtrl_l265_2) begin
|
|
bubbleInserter_timings_banks_2_active_counter <= 3'b001;
|
|
end
|
|
if(when_SdramCtrl_l265_3) begin
|
|
bubbleInserter_timings_banks_3_active_counter <= 3'b001;
|
|
end
|
|
end
|
|
end
|
|
SdramCtrlBackendTask_PRECHARGE_ALL : begin
|
|
if(bubbleInserter_cmd_ready) begin
|
|
if(when_SdramCtrl_l265_4) begin
|
|
bubbleInserter_timings_banks_0_active_counter <= 3'b001;
|
|
end
|
|
end
|
|
end
|
|
SdramCtrlBackendTask_PRECHARGE_SINGLE : begin
|
|
if(bubbleInserter_cmd_ready) begin
|
|
if(when_Utils_l1017) begin
|
|
if(when_SdramCtrl_l265_5) begin
|
|
bubbleInserter_timings_banks_0_active_counter <= 3'b001;
|
|
end
|
|
end
|
|
if(when_Utils_l1017_1) begin
|
|
if(when_SdramCtrl_l265_6) begin
|
|
bubbleInserter_timings_banks_1_active_counter <= 3'b001;
|
|
end
|
|
end
|
|
if(when_Utils_l1017_2) begin
|
|
if(when_SdramCtrl_l265_7) begin
|
|
bubbleInserter_timings_banks_2_active_counter <= 3'b001;
|
|
end
|
|
end
|
|
if(when_Utils_l1017_3) begin
|
|
if(when_SdramCtrl_l265_8) begin
|
|
bubbleInserter_timings_banks_3_active_counter <= 3'b001;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
SdramCtrlBackendTask_REFRESH : begin
|
|
if(bubbleInserter_cmd_ready) begin
|
|
if(when_SdramCtrl_l265_9) begin
|
|
bubbleInserter_timings_banks_0_active_counter <= 3'b101;
|
|
end
|
|
if(when_SdramCtrl_l265_10) begin
|
|
bubbleInserter_timings_banks_1_active_counter <= 3'b101;
|
|
end
|
|
if(when_SdramCtrl_l265_11) begin
|
|
bubbleInserter_timings_banks_2_active_counter <= 3'b101;
|
|
end
|
|
if(when_SdramCtrl_l265_12) begin
|
|
bubbleInserter_timings_banks_3_active_counter <= 3'b101;
|
|
end
|
|
end
|
|
end
|
|
SdramCtrlBackendTask_ACTIVE : begin
|
|
if(bubbleInserter_cmd_ready) begin
|
|
if(when_SdramCtrl_l265_13) begin
|
|
bubbleInserter_timings_write_counter <= 3'b001;
|
|
end
|
|
bubbleInserter_timings_read_counter <= 1'b1;
|
|
if(when_Utils_l1017_4) begin
|
|
if(when_SdramCtrl_l265_14) begin
|
|
bubbleInserter_timings_banks_0_precharge_counter <= 3'b100;
|
|
end
|
|
end
|
|
if(when_Utils_l1017_5) begin
|
|
if(when_SdramCtrl_l265_15) begin
|
|
bubbleInserter_timings_banks_1_precharge_counter <= 3'b100;
|
|
end
|
|
end
|
|
if(when_Utils_l1017_6) begin
|
|
if(when_SdramCtrl_l265_16) begin
|
|
bubbleInserter_timings_banks_2_precharge_counter <= 3'b100;
|
|
end
|
|
end
|
|
if(when_Utils_l1017_7) begin
|
|
if(when_SdramCtrl_l265_17) begin
|
|
bubbleInserter_timings_banks_3_precharge_counter <= 3'b100;
|
|
end
|
|
end
|
|
if(when_Utils_l1017_8) begin
|
|
if(when_SdramCtrl_l265_18) begin
|
|
bubbleInserter_timings_banks_0_active_counter <= 3'b101;
|
|
end
|
|
end
|
|
if(when_Utils_l1017_9) begin
|
|
if(when_SdramCtrl_l265_19) begin
|
|
bubbleInserter_timings_banks_1_active_counter <= 3'b101;
|
|
end
|
|
end
|
|
if(when_Utils_l1017_10) begin
|
|
if(when_SdramCtrl_l265_20) begin
|
|
bubbleInserter_timings_banks_2_active_counter <= 3'b101;
|
|
end
|
|
end
|
|
if(when_Utils_l1017_11) begin
|
|
if(when_SdramCtrl_l265_21) begin
|
|
bubbleInserter_timings_banks_3_active_counter <= 3'b101;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
SdramCtrlBackendTask_READ : begin
|
|
if(bubbleInserter_cmd_ready) begin
|
|
if(when_SdramCtrl_l265_22) begin
|
|
bubbleInserter_timings_write_counter <= 3'b100;
|
|
end
|
|
end
|
|
end
|
|
default : begin
|
|
if(bubbleInserter_cmd_ready) begin
|
|
if(when_Utils_l1017_12) begin
|
|
if(when_SdramCtrl_l265_23) begin
|
|
bubbleInserter_timings_banks_0_precharge_counter <= 3'b001;
|
|
end
|
|
end
|
|
if(when_Utils_l1017_13) begin
|
|
if(when_SdramCtrl_l265_24) begin
|
|
bubbleInserter_timings_banks_1_precharge_counter <= 3'b001;
|
|
end
|
|
end
|
|
if(when_Utils_l1017_14) begin
|
|
if(when_SdramCtrl_l265_25) begin
|
|
bubbleInserter_timings_banks_2_precharge_counter <= 3'b001;
|
|
end
|
|
end
|
|
if(when_Utils_l1017_15) begin
|
|
if(when_SdramCtrl_l265_26) begin
|
|
bubbleInserter_timings_banks_3_precharge_counter <= 3'b001;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
if(chip_remoteCke) begin
|
|
_zz_chip_readHistory_1 <= _zz_chip_readHistory_0;
|
|
end
|
|
if(chip_remoteCke) begin
|
|
_zz_chip_readHistory_2 <= _zz_chip_readHistory_1;
|
|
end
|
|
if(chip_remoteCke) begin
|
|
_zz_chip_readHistory_3 <= _zz_chip_readHistory_2;
|
|
end
|
|
if(chip_remoteCke) begin
|
|
_zz_chip_readHistory_4 <= _zz_chip_readHistory_3;
|
|
end
|
|
if(chip_remoteCke) begin
|
|
_zz_chip_readHistory_5 <= _zz_chip_readHistory_4;
|
|
end
|
|
chip_sdramCkeInternal <= chip_sdramCkeNext;
|
|
chip_sdramCkeInternal_regNext <= chip_sdramCkeInternal;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
case(frontend_state)
|
|
SdramCtrlFrontendState_BOOT_PRECHARGE : begin
|
|
end
|
|
SdramCtrlFrontendState_BOOT_REFRESH : begin
|
|
end
|
|
SdramCtrlFrontendState_BOOT_MODE : begin
|
|
end
|
|
default : begin
|
|
if(!refresh_pending) begin
|
|
if(io_bus_cmd_valid) begin
|
|
if(!when_SdramCtrl_l224) begin
|
|
if(when_SdramCtrl_l229) begin
|
|
if(_zz_2) begin
|
|
frontend_banks_0_row <= frontend_address_row;
|
|
end
|
|
if(_zz_3) begin
|
|
frontend_banks_1_row <= frontend_address_row;
|
|
end
|
|
if(_zz_4) begin
|
|
frontend_banks_2_row <= frontend_address_row;
|
|
end
|
|
if(_zz_5) begin
|
|
frontend_banks_3_row <= frontend_address_row;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
end
|
|
end
|
|
endcase
|
|
if(frontend_rsp_ready) begin
|
|
frontend_rsp_rData_task <= frontend_rsp_payload_task;
|
|
frontend_rsp_rData_bank <= frontend_rsp_payload_bank;
|
|
frontend_rsp_rData_rowColumn <= frontend_rsp_payload_rowColumn;
|
|
frontend_rsp_rData_data <= frontend_rsp_payload_data;
|
|
frontend_rsp_rData_mask <= frontend_rsp_payload_mask;
|
|
frontend_rsp_rData_context <= frontend_rsp_payload_context;
|
|
end
|
|
if(chip_remoteCke) begin
|
|
chip_cmd_payload_context_delay_1 <= chip_cmd_payload_context;
|
|
end
|
|
if(chip_remoteCke) begin
|
|
chip_cmd_payload_context_delay_2 <= chip_cmd_payload_context_delay_1;
|
|
end
|
|
if(chip_remoteCke) begin
|
|
chip_cmd_payload_context_delay_3 <= chip_cmd_payload_context_delay_2;
|
|
end
|
|
if(chip_remoteCke) begin
|
|
chip_cmd_payload_context_delay_4 <= chip_cmd_payload_context_delay_3;
|
|
end
|
|
if(chip_remoteCke) begin
|
|
chip_contextDelayed <= chip_cmd_payload_context_delay_4;
|
|
end
|
|
chip_sdram_CKE <= chip_sdramCkeNext;
|
|
if(chip_remoteCke) begin
|
|
chip_sdram_DQ_read <= io_sdram_DQ_read;
|
|
chip_sdram_CSn <= 1'b0;
|
|
chip_sdram_RASn <= 1'b1;
|
|
chip_sdram_CASn <= 1'b1;
|
|
chip_sdram_WEn <= 1'b1;
|
|
chip_sdram_DQ_write <= chip_cmd_payload_data;
|
|
chip_sdram_DQ_writeEnable <= 16'h0000;
|
|
chip_sdram_DQM[0] <= _zz_chip_sdram_DQM;
|
|
chip_sdram_DQM[1] <= _zz_chip_sdram_DQM;
|
|
if(chip_cmd_valid) begin
|
|
case(chip_cmd_payload_task)
|
|
SdramCtrlBackendTask_PRECHARGE_ALL : begin
|
|
chip_sdram_ADDR[10] <= 1'b1;
|
|
chip_sdram_CSn <= 1'b0;
|
|
chip_sdram_RASn <= 1'b0;
|
|
chip_sdram_CASn <= 1'b1;
|
|
chip_sdram_WEn <= 1'b0;
|
|
end
|
|
SdramCtrlBackendTask_REFRESH : begin
|
|
chip_sdram_CSn <= 1'b0;
|
|
chip_sdram_RASn <= 1'b0;
|
|
chip_sdram_CASn <= 1'b0;
|
|
chip_sdram_WEn <= 1'b1;
|
|
end
|
|
SdramCtrlBackendTask_MODE : begin
|
|
chip_sdram_ADDR <= 13'h0000;
|
|
chip_sdram_ADDR[2 : 0] <= 3'b000;
|
|
chip_sdram_ADDR[3] <= 1'b0;
|
|
chip_sdram_ADDR[6 : 4] <= 3'b011;
|
|
chip_sdram_ADDR[8 : 7] <= 2'b00;
|
|
chip_sdram_ADDR[9] <= 1'b0;
|
|
chip_sdram_BA <= 2'b00;
|
|
chip_sdram_CSn <= 1'b0;
|
|
chip_sdram_RASn <= 1'b0;
|
|
chip_sdram_CASn <= 1'b0;
|
|
chip_sdram_WEn <= 1'b0;
|
|
end
|
|
SdramCtrlBackendTask_ACTIVE : begin
|
|
chip_sdram_ADDR <= chip_cmd_payload_rowColumn;
|
|
chip_sdram_BA <= chip_cmd_payload_bank;
|
|
chip_sdram_CSn <= 1'b0;
|
|
chip_sdram_RASn <= 1'b0;
|
|
chip_sdram_CASn <= 1'b1;
|
|
chip_sdram_WEn <= 1'b1;
|
|
end
|
|
SdramCtrlBackendTask_WRITE : begin
|
|
chip_sdram_ADDR <= chip_cmd_payload_rowColumn;
|
|
chip_sdram_ADDR[10] <= 1'b0;
|
|
chip_sdram_DQ_writeEnable <= 16'hffff;
|
|
chip_sdram_DQ_write <= chip_cmd_payload_data;
|
|
chip_sdram_DQM <= (~ chip_cmd_payload_mask);
|
|
chip_sdram_BA <= chip_cmd_payload_bank;
|
|
chip_sdram_CSn <= 1'b0;
|
|
chip_sdram_RASn <= 1'b1;
|
|
chip_sdram_CASn <= 1'b0;
|
|
chip_sdram_WEn <= 1'b0;
|
|
end
|
|
SdramCtrlBackendTask_READ : begin
|
|
chip_sdram_ADDR <= chip_cmd_payload_rowColumn;
|
|
chip_sdram_ADDR[10] <= 1'b0;
|
|
chip_sdram_BA <= chip_cmd_payload_bank;
|
|
chip_sdram_CSn <= 1'b0;
|
|
chip_sdram_RASn <= 1'b1;
|
|
chip_sdram_CASn <= 1'b0;
|
|
chip_sdram_WEn <= 1'b1;
|
|
end
|
|
default : begin
|
|
chip_sdram_BA <= chip_cmd_payload_bank;
|
|
chip_sdram_ADDR[10] <= 1'b0;
|
|
chip_sdram_CSn <= 1'b0;
|
|
chip_sdram_RASn <= 1'b0;
|
|
chip_sdram_CASn <= 1'b1;
|
|
chip_sdram_WEn <= 1'b0;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
endmodule
|
|
|
|
module StreamFifoLowLatency (
|
|
input wire io_push_valid,
|
|
output wire io_push_ready,
|
|
input wire [15:0] io_push_payload_data,
|
|
input wire io_push_payload_context,
|
|
output wire io_pop_valid,
|
|
input wire io_pop_ready,
|
|
output wire [15:0] io_pop_payload_data,
|
|
output wire io_pop_payload_context,
|
|
input wire io_flush,
|
|
output wire [1:0] io_occupancy,
|
|
output wire [1:0] io_availability,
|
|
input wire clk,
|
|
input wire reset
|
|
);
|
|
|
|
wire fifo_io_push_ready;
|
|
wire fifo_io_pop_valid;
|
|
wire [15:0] fifo_io_pop_payload_data;
|
|
wire fifo_io_pop_payload_context;
|
|
wire [1:0] fifo_io_occupancy;
|
|
wire [1:0] fifo_io_availability;
|
|
|
|
StreamFifo fifo (
|
|
.io_push_valid (io_push_valid ), //i
|
|
.io_push_ready (fifo_io_push_ready ), //o
|
|
.io_push_payload_data (io_push_payload_data[15:0] ), //i
|
|
.io_push_payload_context (io_push_payload_context ), //i
|
|
.io_pop_valid (fifo_io_pop_valid ), //o
|
|
.io_pop_ready (io_pop_ready ), //i
|
|
.io_pop_payload_data (fifo_io_pop_payload_data[15:0]), //o
|
|
.io_pop_payload_context (fifo_io_pop_payload_context ), //o
|
|
.io_flush (io_flush ), //i
|
|
.io_occupancy (fifo_io_occupancy[1:0] ), //o
|
|
.io_availability (fifo_io_availability[1:0] ), //o
|
|
.clk (clk ), //i
|
|
.reset (reset ) //i
|
|
);
|
|
assign io_push_ready = fifo_io_push_ready;
|
|
assign io_pop_valid = fifo_io_pop_valid;
|
|
assign io_pop_payload_data = fifo_io_pop_payload_data;
|
|
assign io_pop_payload_context = fifo_io_pop_payload_context;
|
|
assign io_occupancy = fifo_io_occupancy;
|
|
assign io_availability = fifo_io_availability;
|
|
|
|
endmodule
|
|
|
|
module StreamFifo (
|
|
input wire io_push_valid,
|
|
output wire io_push_ready,
|
|
input wire [15:0] io_push_payload_data,
|
|
input wire io_push_payload_context,
|
|
output reg io_pop_valid,
|
|
input wire io_pop_ready,
|
|
output reg [15:0] io_pop_payload_data,
|
|
output reg io_pop_payload_context,
|
|
input wire io_flush,
|
|
output wire [1:0] io_occupancy,
|
|
output wire [1:0] io_availability,
|
|
input wire clk,
|
|
input wire reset
|
|
);
|
|
|
|
wire [16:0] _zz_logic_ram_port1;
|
|
wire [16:0] _zz_logic_ram_port;
|
|
reg _zz_1;
|
|
reg logic_ptr_doPush;
|
|
wire logic_ptr_doPop;
|
|
wire logic_ptr_full;
|
|
wire logic_ptr_empty;
|
|
reg [1:0] logic_ptr_push;
|
|
reg [1:0] logic_ptr_pop;
|
|
wire [1:0] logic_ptr_occupancy;
|
|
wire [1:0] logic_ptr_popOnIo;
|
|
wire when_Stream_l1205;
|
|
reg logic_ptr_wentUp;
|
|
wire io_push_fire;
|
|
wire logic_push_onRam_write_valid;
|
|
wire [0:0] logic_push_onRam_write_payload_address;
|
|
wire [15:0] logic_push_onRam_write_payload_data_data;
|
|
wire logic_push_onRam_write_payload_data_context;
|
|
wire logic_pop_addressGen_valid;
|
|
wire logic_pop_addressGen_ready;
|
|
wire [0:0] logic_pop_addressGen_payload;
|
|
wire logic_pop_addressGen_fire;
|
|
wire [15:0] logic_pop_async_readed_data;
|
|
wire logic_pop_async_readed_context;
|
|
wire [16:0] _zz_logic_pop_async_readed_data;
|
|
wire logic_pop_addressGen_translated_valid;
|
|
wire logic_pop_addressGen_translated_ready;
|
|
wire [15:0] logic_pop_addressGen_translated_payload_data;
|
|
wire logic_pop_addressGen_translated_payload_context;
|
|
(* ram_style = "distributed" *) reg [16:0] logic_ram [0:1];
|
|
|
|
assign _zz_logic_ram_port = {logic_push_onRam_write_payload_data_context,logic_push_onRam_write_payload_data_data};
|
|
always @(posedge clk) begin
|
|
if(_zz_1) begin
|
|
logic_ram[logic_push_onRam_write_payload_address] <= _zz_logic_ram_port;
|
|
end
|
|
end
|
|
|
|
assign _zz_logic_ram_port1 = logic_ram[logic_pop_addressGen_payload];
|
|
always @(*) begin
|
|
_zz_1 = 1'b0;
|
|
if(logic_push_onRam_write_valid) begin
|
|
_zz_1 = 1'b1;
|
|
end
|
|
end
|
|
|
|
assign when_Stream_l1205 = (logic_ptr_doPush != logic_ptr_doPop);
|
|
assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 2'b10) == 2'b00);
|
|
assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop);
|
|
assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo);
|
|
assign io_push_ready = (! logic_ptr_full);
|
|
assign io_push_fire = (io_push_valid && io_push_ready);
|
|
always @(*) begin
|
|
logic_ptr_doPush = io_push_fire;
|
|
if(logic_ptr_empty) begin
|
|
if(io_pop_ready) begin
|
|
logic_ptr_doPush = 1'b0;
|
|
end
|
|
end
|
|
end
|
|
|
|
assign logic_push_onRam_write_valid = io_push_fire;
|
|
assign logic_push_onRam_write_payload_address = logic_ptr_push[0:0];
|
|
assign logic_push_onRam_write_payload_data_data = io_push_payload_data;
|
|
assign logic_push_onRam_write_payload_data_context = io_push_payload_context;
|
|
assign logic_pop_addressGen_valid = (! logic_ptr_empty);
|
|
assign logic_pop_addressGen_payload = logic_ptr_pop[0:0];
|
|
assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready);
|
|
assign logic_ptr_doPop = logic_pop_addressGen_fire;
|
|
assign _zz_logic_pop_async_readed_data = _zz_logic_ram_port1;
|
|
assign logic_pop_async_readed_data = _zz_logic_pop_async_readed_data[15 : 0];
|
|
assign logic_pop_async_readed_context = _zz_logic_pop_async_readed_data[16];
|
|
assign logic_pop_addressGen_translated_valid = logic_pop_addressGen_valid;
|
|
assign logic_pop_addressGen_ready = logic_pop_addressGen_translated_ready;
|
|
assign logic_pop_addressGen_translated_payload_data = logic_pop_async_readed_data;
|
|
assign logic_pop_addressGen_translated_payload_context = logic_pop_async_readed_context;
|
|
always @(*) begin
|
|
io_pop_valid = logic_pop_addressGen_translated_valid;
|
|
if(logic_ptr_empty) begin
|
|
io_pop_valid = io_push_valid;
|
|
end
|
|
end
|
|
|
|
assign logic_pop_addressGen_translated_ready = io_pop_ready;
|
|
always @(*) begin
|
|
io_pop_payload_data = logic_pop_addressGen_translated_payload_data;
|
|
if(logic_ptr_empty) begin
|
|
io_pop_payload_data = io_push_payload_data;
|
|
end
|
|
end
|
|
|
|
always @(*) begin
|
|
io_pop_payload_context = logic_pop_addressGen_translated_payload_context;
|
|
if(logic_ptr_empty) begin
|
|
io_pop_payload_context = io_push_payload_context;
|
|
end
|
|
end
|
|
|
|
assign logic_ptr_popOnIo = logic_ptr_pop;
|
|
assign io_occupancy = logic_ptr_occupancy;
|
|
assign io_availability = (2'b10 - logic_ptr_occupancy);
|
|
always @(posedge clk or posedge reset) begin
|
|
if(reset) begin
|
|
logic_ptr_push <= 2'b00;
|
|
logic_ptr_pop <= 2'b00;
|
|
logic_ptr_wentUp <= 1'b0;
|
|
end else begin
|
|
if(when_Stream_l1205) begin
|
|
logic_ptr_wentUp <= logic_ptr_doPush;
|
|
end
|
|
if(io_flush) begin
|
|
logic_ptr_wentUp <= 1'b0;
|
|
end
|
|
if(logic_ptr_doPush) begin
|
|
logic_ptr_push <= (logic_ptr_push + 2'b01);
|
|
end
|
|
if(logic_ptr_doPop) begin
|
|
logic_ptr_pop <= (logic_ptr_pop + 2'b01);
|
|
end
|
|
if(io_flush) begin
|
|
logic_ptr_push <= 2'b00;
|
|
logic_ptr_pop <= 2'b00;
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
endmodule
|