132 lines
4.5 KiB
Verilog
132 lines
4.5 KiB
Verilog
`timescale 1ns/1ps
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module Sdram_Tester #(
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parameter TEST_LENGTH = 24'd1048576
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)(
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input wire clk,
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input wire rst_n,
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// --- 连接到 SDRAM 控制器的用户接口 ---
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output reg cmd_valid,
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input wire cmd_ready,
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output reg is_write,
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output reg [23:0] address,
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output wire [15:0] write_data,
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input wire rsp_valid,
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input wire [15:0] rsp_data,
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// --- 外部 LED 状态指示灯 ---
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output reg test_pass, // 绿色 LED，成功后闪烁
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output reg test_fail // 红色 LED，发生错误时常亮
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);
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// ==========================================
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// 状态机定义
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// ==========================================
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localparam S_INIT = 3'd0; // 等待 SDRAM 初始化
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localparam S_WRITE = 3'd1; // 发起单次写命令
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localparam S_READ = 3'd2; // 发起单次读命令 (交替操作)
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localparam S_WAIT_RSP = 3'd3; // 等待读响应并比对
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localparam S_DONE = 3'd4; // 测试成功完成
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localparam S_ERROR = 3'd5; // 数据校验错误
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reg [2:0] state;
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reg [15:0] init_cnt; // 用于上电延时计数
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reg [23:0] test_addr; // 当前正在测试的地址
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// 新增：用于控制 LED 闪烁的 26 位计数器
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reg [25:0] blink_cnt;
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// ==========================================
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// 测试数据生成器
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// ==========================================
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// 地址低16位 异或 0x5A5A，保证每个地址的数据唯一且具有翻转特性
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wire [15:0] expected_data = test_addr[15:0] ^ 16'h5A5A;
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assign write_data = expected_data;
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// ==========================================
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// 主状态机控制逻辑
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// ==========================================
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= S_INIT;
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init_cnt <= 16'd0;
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test_addr <= 24'd0;
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blink_cnt <= 26'd0; // 复位闪烁计数器
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cmd_valid <= 1'b0;
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is_write <= 1'b0;
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address <= 24'd0;
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test_pass <= 1'b0;
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test_fail <= 1'b0;
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end else begin
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case (state)
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// 1. 等待初始化 (200us @ 100MHz)
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S_INIT: begin
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if (init_cnt < 16'd20000) begin
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init_cnt <= init_cnt + 1'b1;
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end else begin
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state <= S_WRITE;
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end
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end
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// 2. 写操作
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S_WRITE: begin
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cmd_valid <= 1'b1;
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is_write <= 1'b1;
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address <= test_addr;
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if (cmd_valid && cmd_ready) begin
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cmd_valid <= 1'b0;
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state <= S_READ;
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end
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end
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// 3. 读操作
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S_READ: begin
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cmd_valid <= 1'b1;
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is_write <= 1'b0;
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address <= test_addr;
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if (cmd_valid && cmd_ready) begin
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cmd_valid <= 1'b0;
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state <= S_WAIT_RSP;
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end
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end
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// 4. 数据比对
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S_WAIT_RSP: begin
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if (rsp_valid) begin
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if (rsp_data == expected_data) begin
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if (test_addr == TEST_LENGTH - 1) begin
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state <= S_DONE;
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end else begin
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test_addr <= test_addr + 2'b11;
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state <= S_WRITE;
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end
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end else begin
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state <= S_ERROR;
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end
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end
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end
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// 5. 测试通过：LED 闪烁逻辑
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S_DONE: begin
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// 计数器不断累加
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blink_cnt <= blink_cnt + 1'b1;
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test_pass <= blink_cnt[25];
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test_fail <= 1'b0;
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end
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// 6. 测试失败：红灯常亮
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S_ERROR: begin
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test_pass <= 1'b0;
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test_fail <= 1'b1;
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end
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default: state <= S_INIT;
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endcase
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end
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end
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endmodule |